公开(公告)号：US20200321674A1

公开(公告)日：2020-10-08

申请号：US16305355

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Hungying Lo ,  Bok Eng Cheah

IPC: H01P3/08 ,  H01L23/498 ,  H05K1/02 ,  H01P3/02

Abstract: One embodiment provides an apparatus. The apparatus includes a first signal trace and a current return path. The current return path includes a plurality of portions. The plurality of portions includes a first portion, a second portion and a third portion. The first portion is included in a first power plane. The second portion is included in a second power plane coplanar with the first power plane and separated from the first power plane by a split. The third portion spans the split and is included in a reference voltage plane. The reference voltage plane is coplanar with the first signal trace. The reference voltage plane is separated from the first power plane and the second power plane by a dielectric material.

公开(公告)号：US20190311978A1

公开(公告)日：2019-10-10

申请号：US16280850

申请日：2019-02-20

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Ping Ping Ooi ,  Shaw Fong Wong ,  Jackson Chung Peng Kong ,  Hungying Lo

IPC: H01L23/498 ,  H05K1/18 ,  H01L23/00 ,  H01L25/16 ,  H01L21/48 ,  H05K3/34

Abstract: A semiconductor package substrate includes a composite and stacked vertical interconnect on a land side of the substrate. The composite and stacked vertical interconnect includes a smaller contact end against the semiconductor package substrate, and a larger contact end for board mounting.