公开(公告)号：US20190205730A1

公开(公告)日：2019-07-04

申请号：US16299014

申请日：2019-03-11

Applicant: Intel Corporation

Inventor： Huseyin E. SUMBUL ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Christopher Knag ,  Ram Krishnamurthy

IPC: G06N3/04 ,  G06N3/08 ,  G06N3/063

CPC classification number: G06N3/049 ,  G06N3/063 ,  G06N3/088

Abstract: A neuromorphic computing system is provided which comprises: a synapse core; and a pre-synaptic neuron, a first post-synaptic neuron, and a second post-synaptic neuron coupled to the synaptic core, wherein the synapse core is to: receive a request from the pre-synaptic neuron, generate, in response to the request, a first address of the first post-synaptic neuron and a second address of the second post-synaptic neuron, wherein the first address and the second address are not stored in the synapse core prior to receiving the request.

公开(公告)号：US20180181861A1

公开(公告)日：2018-06-28

申请号：US15392407

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Huseyin E. SUMBUL ,  Gregory K. CHEN ,  Raghavan KUMAR ,  Phil C. Knag ,  Ram Krishnamurthy

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

CPC classification number: G06N3/049 ,  G06N3/063 ,  G06N3/088

Abstract: A neuromorphic computing system is provided which comprises: a synapse core; and a pre-synaptic neuron, a first post-synaptic neuron, and a second post-synaptic neuron coupled to the synaptic core, wherein the synapse core is to: receive a request from the pre-synaptic neuron, generate, in response to the request, a first address of the first post-synaptic neuron and a second address of the second post-synaptic neuron, wherein the first address and the second address are not stored in the synapse core prior to receiving the request.