公开(公告)号：US20250005100A1

公开(公告)日：2025-01-02

申请号：US18217564

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Raghavan KUMAR ,  AppaRao CHALLAGUNDLA ,  Sanu K. MATHEW ,  Christopher B. WILKERSON ,  Adish VARTAK ,  Sachin TANEJA ,  Minxuan ZHOU ,  Lalith Dharmesh KETHARESWARAN

IPC: G06F17/14

Abstract: Examples include techniques for contention-free routing for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations routed through a parallel processing device. Examples include a tile array that includes a plurality of tiles arranged in a 2-dimensional mesh interconnect-based architecture. Each tile includes a plurality of compute elements configured to execute NTT or iNTT computations associated with a fully homomorphic encryption workload.

公开(公告)号：US20190303750A1

公开(公告)日：2019-10-03

申请号：US16443548

申请日：2019-06-17

Applicant: Intel Corporation

Inventor： Raghavan KUMAR ,  Gregory K. CHEN ,  Huseyin Ekin SUMBUL ,  Phil KNAG ,  Ram KRISHNAMURTHY

IPC: G06N3/063 ,  G06F7/544 ,  G06N3/08

Abstract: Examples described herein relate to a neural network whose weights from a matrix are selected from a set of weights stored in a memory on-chip with a processing engine for generating multiply and carry operations. The number of weights in the set of weights stored in the memory can be less than a number of weights in the matrix thereby reducing an amount of memory used to store weights in a matrix. The weights in the memory can be generated in training using gradients from back propagation. Weights in the memory can be selected using a tabulation hash calculation on entries in a table.

公开(公告)号：US20230334006A1

公开(公告)日：2023-10-19

申请号：US18212079

申请日：2023-06-20

Applicant: Intel Corporation

Inventor： Huseyin Ekin SUMBUL ,  Gregory K. CHEN ,  Phil KNAG ,  Raghavan KUMAR ,  Ram KRISHNAMURTHY

IPC: G06F15/80 ,  G06F17/15 ,  G06N3/063

CPC classification number: G06F15/8046 ,  G06F17/153 ,  G06N3/063

Abstract: A compute near memory (CNM) convolution accelerator enables a convolutional neural network (CNN) to use dedicated acceleration to achieve efficient in-place convolution operations with less impact on memory and energy consumption. A 2D convolution operation is reformulated as 1D row-wise convolution. The 1D row-wise convolution enables the CNM convolution accelerator to process input activations row-by-row, while using the weights one-by-one. Lightweight access circuits provide the ability to stream both weights and input rows as vectors to MAC units, which in turn enables modules of the CNM convolution accelerator to implement convolution for both [1×1] and chosen [n×n] sized filters.

公开(公告)号：US20230297819A1

公开(公告)日：2023-09-21

申请号：US18201291

申请日：2023-05-24

Applicant: Intel Corporation

Inventor： Ram KRISHNAMURTHY ,  Gregory K. CHEN ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin Ekin SUMBUL ,  Deepak Vinayak KADETOTAD

IPC: G06N3/063 ,  G06F17/16 ,  G06N3/04 ,  G06F7/544

CPC classification number: G06N3/063 ,  G06F17/16 ,  G06N3/04 ,  G06F7/5443

Abstract: An apparatus is described. The apparatus includes a circuit to process a binary neural network. The circuit includes an array of processing cores, wherein, processing cores of the array of processing cores are to process different respective areas of a weight matrix of the binary neural network. The processing cores each include add circuitry to add only those weights of an i layer of the binary neural network that are to be effectively multiplied by a non zero nodal output of an i−1 layer of the binary neural network.

公开(公告)号：US20200034148A1

公开(公告)日：2020-01-30

申请号：US16586975

申请日：2019-09-28

Applicant: Intel Corporation

Inventor： Huseyin Ekin SUMBUL ,  Gregory K. CHEN ,  Phil KNAG ,  Raghavan KUMAR ,  Ram KRISHNAMURTHY

IPC: G06F9/30 ,  G06F9/54 ,  G06F17/15 ,  G06F15/80 ,  G06F7/544 ,  G06N3/04

Abstract: A compute near memory (CNM) convolution accelerator enables a convolutional neural network (CNN) to use dedicated acceleration to achieve efficient in-place convolution operations with less impact on memory and energy consumption. A 2D convolution operation is reformulated as 1D row-wise convolution. The 1D row-wise convolution enables the CNM convolution accelerator to process input activations row-by-row, while using the weights one-by-one. Lightweight access circuits provide the ability to stream both weights and input row as vectors to MAC units, which in turn enables modules of the CNM convolution accelerator to implement convolution for both [1×1] and chosen [n×n] sized filters.

公开(公告)号：US20190065151A1

公开(公告)日：2019-02-28

申请号：US16145569

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Gregory K. CHEN ,  Raghavan KUMAR ,  Huseyin Ekin SUMBUL ,  Phil KNAG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Ian A. YOUNG

IPC: G06F7/544 ,  G06F9/30 ,  G06F7/501 ,  G06F17/16

Abstract: A memory device that includes a plurality subarrays of memory cells to store static weights and a plurality of digital full-adder circuits between subarrays of memory cells is provided. The digital full-adder circuit in the memory device eliminates the need to move data from a memory device to a processor to perform machine learning calculations. Rows of full-adder circuits are distributed between sub-arrays of memory cells to increase the effective memory bandwidth and reduce the time to perform matrix-vector multiplications in the memory device by performing bit-serial dot-product primitives in the form of accumulating m 1-bit x n-bit multiplications.

公开(公告)号：US20190042949A1

公开(公告)日：2019-02-07

申请号：US16147143

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Ian A. YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Gregory K. CHEN ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin Ekin SUMBUL

IPC: G06N3/10 ,  G06F17/50 ,  G06N3/063

Abstract: A semiconductor chip is described. The semiconductor chip includes a compute-in-memory (CIM) circuit to implement a neural network in hardware. The semiconductor chip also includes at least one output that presents samples of voltages generated at a node of the CIM circuit in response to a range of neural network input values applied to the CIM circuit to optimize the CIM circuit for the neural network.

公开(公告)号：US20250005101A1

公开(公告)日：2025-01-02

申请号：US18217565

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Sachin TANEJA ,  Sanu K. MATHEW ,  Raghavan KUMAR ,  Nojan SHEYBANI ,  Vikram B. SURESH

IPC: G06F17/14

Abstract: Examples include techniques for twiddle factor generation for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations by a compute element. The compute element can be included in a parallel processing device. Examples include receiving information to generate a twiddle factor for use by the compute element to execute an NTT or an iNTT computation for an N-degree polynomial, obtain data for a power of 2 of a root of unity from a memory resident on a same chip or die as the compute element and generate the twiddle factor using the obtained data based, at least in part, on the received information.

公开(公告)号：US20220012581A1

公开(公告)日：2022-01-13

申请号：US17484828

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Abhishek SHARMA ,  Jack T. KAVALIEROS ,  Ian A. YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Uygar AVCI ,  Gregory K. CHEN ,  Amrita MATHURIYA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin Ekin SUMBUL ,  Nazila HARATIPOUR ,  Van H. LE

IPC: G06N3/063 ,  H01L27/108 ,  H01L27/11502 ,  G06N3/04 ,  G06F17/16 ,  H01L27/11 ,  G11C11/54 ,  G11C7/10

Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

公开(公告)号：US20200097807A1

公开(公告)日：2020-03-26

申请号：US16697616

申请日：2019-11-27

Applicant: Intel Corporation

Inventor： Phil KNAG ,  Gregory K. CHEN ,  Raghavan KUMAR ,  Huseyin Ekin SUMBUL ,  Ram KRISHNAMURTHY

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04

Abstract: A compute near memory binary neural network accelerator with digital circuits that achieves energy efficiencies comparable to or surpassing a compute near memory binary neural network accelerator with analog circuits is provided. The compute near memory binary neural network accelerator with digital circuits is more process scalable, robust to process, voltage and temperature variations, and immune to circuit noise.