公开(公告)号：US20230071117A1

公开(公告)日：2023-03-09

申请号：US17987687

申请日：2022-11-15

Applicant: Intel Corporation

Inventor： Hussein ALAMEER ,  Bill NALE ,  George VERGIS ,  Rajat AGARWAL

IPC: G06F3/06

Abstract: A memory module has a registering clock driver (RCD) that issues two column address strobe (CAS) commands with a single memory access command to exchange a double amount of data per dynamic random access memory (DRAM) device per memory access command. With double the amount of data per DRAM device, the memory module can provide double the pseudo channels as compared to a memory module where a single CAS command is issued per access command. The RCD can time division multiplex separate first commands for a first group of the DRAM devices from second commands for a second group of the DRAM devices on the command/address (CA) bus.

公开(公告)号：US20190004909A1

公开(公告)日：2019-01-03

申请号：US15640182

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Hussein ALAMEER ,  Uksong KANG ,  Kjersten E. CRISS ,  Rajat AGARWAL ,  Wei WU ,  John B. HALBERT

IPC: G06F11/16 ,  H01L25/065 ,  G11C5/02 ,  G11C7/24

Abstract: A stacked memory chip device is described. The stacked memory chip device includes a plurality of stacked memory chips. The stacked memory chip device includes read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips. The stacked memory chip device includes data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive information of a particular one of the cache lines is not stored in a same memory chip with the respective substantive information.