SHARED PARITY CHECK FOR CORRECTING MEMORY ERRORS

    公开(公告)号:US20190042358A1

    公开(公告)日:2019-02-07

    申请号:US15890204

    申请日:2018-02-06

    Abstract: Examples include techniques for implementing read and write operations between a memory controller and a memory device. In an embodiment, the memory controller is configured to receive data bits to write to the memory device, to determine, using a memory controller ECC component and the data bits, a plurality of memory controller ECC check bits and one or more parity bits, to append the memory controller ECC check bits and the one or more parity bits to the data bits, and to send the data bits, the memory controller ECC check bits, and the one or more parity bits to the memory device during a write operation. In an embodiment, the memory controller is configured to receive the data bits and the memory controller ECC check bits from the memory device, to check the data bits against the memory controller ECC check bits and correct errors detected, and to return the data bits during a read operation.

    STACKED MEMORY CHIP DEVICE WITH ENHANCED DATA PROTECTION CAPABILITY

    公开(公告)号:US20190004909A1

    公开(公告)日:2019-01-03

    申请号:US15640182

    申请日:2017-06-30

    Abstract: A stacked memory chip device is described. The stacked memory chip device includes a plurality of stacked memory chips. The stacked memory chip device includes read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips. The stacked memory chip device includes data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive information of a particular one of the cache lines is not stored in a same memory chip with the respective substantive information.

    END-TO-END DATA PROTECTION FOR COMPUTE IN MEMORY (CIM)/COMPUTE NEAR MEMORY (CNM)

    公开(公告)号:US20220107867A1

    公开(公告)日:2022-04-07

    申请号:US17553623

    申请日:2021-12-16

    Abstract: A near memory compute system includes multiple computation nodes, such as nodes for parallel distributed processing. The nodes include a memory device to store data and compute hardware to perform a computation on the data. Error correction code (ECC) logic performs ECC on the data prior to computation on the data by the compute hardware. The node also includes residue check logic to perform a residue check on a result of the computation.

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