公开(公告)号：US20190042358A1

公开(公告)日：2019-02-07

申请号：US15890204

申请日：2018-02-06

Applicant: Intel Corporation

Inventor： Kjersten E. CRISS ,  Wei WU

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: Examples include techniques for implementing read and write operations between a memory controller and a memory device. In an embodiment, the memory controller is configured to receive data bits to write to the memory device, to determine, using a memory controller ECC component and the data bits, a plurality of memory controller ECC check bits and one or more parity bits, to append the memory controller ECC check bits and the one or more parity bits to the data bits, and to send the data bits, the memory controller ECC check bits, and the one or more parity bits to the memory device during a write operation. In an embodiment, the memory controller is configured to receive the data bits and the memory controller ECC check bits from the memory device, to check the data bits against the memory controller ECC check bits and correct errors detected, and to return the data bits during a read operation.

公开(公告)号：US20180090201A1

公开(公告)日：2018-03-29

申请号：US15276588

申请日：2016-09-26

Applicant: INTEL CORPORATION

Inventor： Wei WU ,  Jawad B. KHAN ,  Sanjeev N. TRIKA ,  Yi ZOU

IPC: G11C11/56 ,  G11C29/52 ,  G06F11/10

CPC classification number: G11C11/5628 ,  G06F11/1044 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3427 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

Abstract: Provided are a method and apparatus for programming non-volatile memory using a multi-cell storage cell group to provide error location information for retention errors. Each storage cell in the non-volatile memory is programmed with threshold voltage levels and each storage cell is programmed from bits from a plurality of pages. A memory controller organizes the storage cells into storage cell groups, each storing m bits of information programmed with the threshold voltage levels. A determination is made of one threshold voltage level to use for each of the storage cells in the storage cell group to program a selected k bits in the storage cell group with threshold voltage levels defining one of a plurality of valid states. The threshold voltage levels for at least one of the storage cells of the storage cell group in any two valid states differ by at least two threshold voltage levels.

公开(公告)号：US20190004909A1

公开(公告)日：2019-01-03

申请号：US15640182

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Hussein ALAMEER ,  Uksong KANG ,  Kjersten E. CRISS ,  Rajat AGARWAL ,  Wei WU ,  John B. HALBERT

IPC: G06F11/16 ,  H01L25/065 ,  G11C5/02 ,  G11C7/24

Abstract: A stacked memory chip device is described. The stacked memory chip device includes a plurality of stacked memory chips. The stacked memory chip device includes read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips. The stacked memory chip device includes data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive information of a particular one of the cache lines is not stored in a same memory chip with the respective substantive information.

公开(公告)号：US20180040367A1

公开(公告)日：2018-02-08

申请号：US15228699

申请日：2016-08-04

Applicant: INTEL CORPORATION

Inventor： Wei WU ,  Yi ZOU ,  Jawad B. KHAN ,  Xin GUO

IPC: G11C11/56 ,  G06F3/06

CPC classification number: G11C11/5628 ,  G06F3/0608 ,  G06F3/0661 ,  G06F3/0688 ,  G11C7/1006 ,  G11C11/5642 ,  G11C16/10 ,  G11C2211/5641 ,  G11C2211/5648

Abstract: Provided are a method and apparatus for endurance friendly programming using lower voltage thresholds. A non-volatile memory has storage cells organized as pages programmed using a first number of threshold voltage levels. The storage cells are organized into storage cell groups to which data is written. Each storage cell group is programmed to store a first number of bits of information. A memory controller selects a second number of bits of information from pages less than the first number of bits of information. The memory controller programs the storage cells of the storage cell group using threshold voltage levels from a second number of threshold voltage levels, wherein the second number of threshold voltage levels is less than the first number of threshold voltage levels and comprises a lowest of the first number of threshold voltage levels.

公开(公告)号：US20180039429A1

公开(公告)日：2018-02-08

申请号：US15228729

申请日：2016-08-04

Applicant: INTEL CORPORATION

Inventor： Wei WU ,  Yi ZOU ,  Jawad B. KHAN ,  Xin GUO

IPC: G06F3/06 ,  G06F12/1009 ,  G11C11/56

CPC classification number: G06F3/0616 ,  G06F3/0644 ,  G06F3/0688 ,  G06F12/1009 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/7201 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C2211/5641 ,  G11C2211/5648

Abstract: Provided are an apparatus, method, and system for programming a multi-cell storage cell group. A non-volatile memory has storage cells. Each storage cell is programmed with information using a plurality of threshold voltage levels and each storage cell is programmed from bits from a plurality of pages. A memory controller is configured to program the storage cells and to organize the storage cells in the non-volatile memory into storage cell groups. Each storage cell group stores a number of bits of information and each of the storage cells in each of the storage cell groups is programmed with the plurality of threshold voltage levels. The memory controller selects bits from the pages to write for one storage cell group and determines at least one threshold voltage level to use for each of the storage cells in the storage cell group to program the selected bits in the storage cell group.

公开(公告)号：US20170178697A1

公开(公告)日：2017-06-22

申请号：US14975298

申请日：2015-12-18

Applicant: INTEL CORPORATION

Inventor： Wei WU ,  Shigeki TOMISHIMA ,  Shih-Lien L. LU

IPC: G11C7/06 ,  G11C11/406 ,  G06F13/40 ,  G11C7/10 ,  G06F13/16 ,  G06F13/42

CPC classification number: G11C7/06 ,  G06F13/1678 ,  G06F13/4018 ,  G06F13/4282 ,  G11C7/1048 ,  G11C7/1072 ,  G11C11/40618 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/105 ,  G11C2207/107

Abstract: Provided is memory device and a memory bank, comprising a global data bus, and a local data bus split into two parts, wherein the local data bus is configurable to direct signals to the global data bus. Provided also is a method in which signals are received in a local data bus that is split into two parts, and the signals are directed from the local data bus to the global data bus. Provided also is a computational device comprised of a processor and the memory device.

公开(公告)号：US20170177526A1

公开(公告)日：2017-06-22

申请号：US14975305

申请日：2015-12-18

Applicant: INTEL CORPORATION

Inventor： Wei WU ,  Shigeki TOMISHIMA ,  Shih-Lien L. LU

IPC: G06F13/40 ,  G11C11/4093 ,  G06F13/16 ,  G11C11/4091

CPC classification number: G06F13/4022 ,  G06F13/1668 ,  G11C5/025 ,  G11C5/063 ,  G11C7/06 ,  G11C7/1048 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/105 ,  G11C2207/107

Abstract: Provided are a memory device and a memory bank comprised of a local data bus, a segmented global data bus coupled to the local data bus, and a section select switch that is configurable to direct a signal from the local data bus to either end of the segmented global data bus. Provided also is a computational device comprising a processor and the memory device and optionally a display. Provided also is a method in which a signal is received from a local data bus, and a section select switch is configured to direct the signal from the local data bus to either end of a segmented global data bus.

公开(公告)号：US20240020197A1

公开(公告)日：2024-01-18

申请号：US18372525

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Wei WU ,  Hechen WANG

IPC: G06F11/10 ,  G06F11/07 ,  G06F17/16

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F17/16

Abstract: Circuitry for a compute-in-memory (CiM) circuit or structure arranged to detect bit errors in a group of memory cells based on a summation of binary 1's included in at least one weight matrix stored to the group of memory cells, a parity value stored to another group of memory cells and a comparison of the summation or the parity value to an expected value.

公开(公告)号：US20240013850A1

公开(公告)日：2024-01-11

申请号：US18372482

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Wei WU ,  Hechen WANG

IPC: G11C29/52 ,  G11C7/18 ,  G06F7/492

CPC classification number: G11C29/52 ,  G11C7/18 ,  G06F7/4925

Abstract: A compute-in-memory (CiM) circuit or structure arranged to detect errors. Examples include detecting errors associated with weight bits stored to computational nodes included in a CiM circuit or structure based on use of complimented bit values. Examples also include detecting errors in the CiM circuit or structure based on using at least some computational nodes included in an array of computational nodes to monitor for the errors during generation of computation results by other computational nodes included in the array.

公开(公告)号：US20220107867A1

公开(公告)日：2022-04-07

申请号：US17553623

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Wei WU ,  Carlos TOKUNAGA ,  Gregory K. CHEN

IPC: G06F11/10

Abstract: A near memory compute system includes multiple computation nodes, such as nodes for parallel distributed processing. The nodes include a memory device to store data and compute hardware to perform a computation on the data. Error correction code (ECC) logic performs ECC on the data prior to computation on the data by the compute hardware. The node also includes residue check logic to perform a residue check on a result of the computation.