公开(公告)号：US20220230972A1

公开(公告)日：2022-07-21

申请号：US17714944

申请日：2022-04-06

Applicant: Intel Corporation

Inventor： Digvijay A. RAORANE ,  Ian En Yoon CHIN ,  Daniel N. SOBIESKI

IPC: H01L23/00 ,  H01L21/50 ,  H01L23/498

Abstract: Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.

公开(公告)号：US20200251426A1

公开(公告)日：2020-08-06

申请号：US16849707

申请日：2020-04-15

Applicant: Intel Corporation

Inventor： Digvijay A. RAORANE ,  Ian En Yoon CHIN ,  Daniel N. SOBIESKI

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/50

Abstract: Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.

公开(公告)号：US20180301423A1

公开(公告)日：2018-10-18

申请号：US15948958

申请日：2018-04-09

Applicant: Intel Corporation

Inventor： Digvijay A. RORANE ,  Ian En Yoon CHIN ,  Daniel N. SOBIESKI

IPC: H01L23/00 ,  H01L21/50 ,  H01L23/498

Abstract: Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.