公开(公告)号：US20190287942A1

公开(公告)日：2019-09-19

申请号：US16349543

申请日：2016-12-29

申请人： Intel Corporation

发明人： Debendra MALLIK ,  Digvijay A. RAORANE ,  Ravindranath Vithal MAHAJAN ,  Mitul Bharat MODI

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/42 ,  H01L23/48 ,  H01L21/768 ,  H01L21/822

摘要： Semiconductor packages including passive support wafers, and methods of fabricating such semiconductor packages, are described. In an example, a semiconductor package includes a passive support wafer mounted on several active dies. The active dies may be attached to an active die wafer, and the passive support wafer may include a monolithic form to stabilize the active dies and active die wafer during processing and use. Furthermore, the passive support wafer may include a monolith of non-polymeric material to transfer and uniformly distribute heat generated by the active dies.

公开(公告)号：US20230197636A1

公开(公告)日：2023-06-22

申请号：US18112431

申请日：2023-02-21

申请人： Intel Corporation

发明人： Debendra MALLIK ,  Digvijay A. RAORANE

IPC分类号： H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L25/065 ,  H01L25/16 ,  H01L25/00

CPC分类号： H01L23/562 ,  H01L23/16 ,  H01L23/3121 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06582

摘要： An electronic package technology is disclosed. A first active die can be mountable to and electrically coupleable to a package substrate. A second active die can be disposed on a top side of the first active die, the second active die being electrically coupleable to one or both of the first active die and the package substrate. At least one open space can be available on the top side of the first active die. At least a portion of a stiffener can substantially fill the at least one open space available on the top side of the first active die.

公开(公告)号：US20210057348A1

公开(公告)日：2021-02-25

申请号：US16650292

申请日：2017-12-19

申请人： Intel Corporation

发明人： Ehren HWANG ,  Christopher M. PELTO ,  Seshu V. SATTIRAJU ,  Shravan GOWRISHANKAR ,  Zachary A. ZELL ,  Digvijay A. RAORANE

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

摘要： Disclosed are barrier materials between bumps and pads, and related devices and methods. A semiconductor device includes an interconnect, a top material, a pad on the interconnect and at least a portion of the top material, a bump on the pad, and a barrier material between the pad and the bump. The top material defines a via therethrough to the interconnect. The pad includes electrically conductive material. The bump includes electrically conductive material. The bump is configured to electrically connect the interconnect to another device. The barrier material is between the pad and the bump. The barrier material includes a conductive material that is resistant to electromigration, intermetallic compound reaction, or both electromigration and intermetallic compound reaction.

公开(公告)号：US20200251426A1

公开(公告)日：2020-08-06

申请号：US16849707

申请日：2020-04-15

申请人： Intel Corporation

发明人： Digvijay A. RAORANE ,  Ian En Yoon CHIN ,  Daniel N. SOBIESKI

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L21/50

摘要： Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.

公开(公告)号：US20180174999A1

公开(公告)日：2018-06-21

申请号：US15385673

申请日：2016-12-20

申请人： INTEL CORPORATION

发明人： Mitul MODI ,  Digvijay A. RAORANE

IPC分类号： H01L25/065 ,  H01L27/1157 ,  H01L27/11524 ,  H01L21/78 ,  H01L23/00

CPC分类号： H01L25/0652 ,  H01L24/03 ,  H01L24/08 ,  H01L2224/0331 ,  H01L2224/08501 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06551

摘要： A stacked-chip assembly including an IC chip or die that is electrically interconnected to another chip and/or a substrate by one or more traces that are coupled through sidewalls of the chip. Electrical traces extending over a sidewall of the chip may contact metal traces of one or more die interconnect levels that intersect the chip edge. Following chip fabrication, singulation may expose a metal trace that intersects the chip sidewall. Following singulation, a conductive sidewall interconnect trace formed over the chip sidewall is to couple the exposed trace to a top or bottom side of a chip or substrate. The sidewall interconnect trace may be further coupled to a ground, signal, or power rail. The sidewall interconnect trace may terminate with a bond pad to which another chip, substrate, or wire lead is bonded. The sidewall interconnect trace may terminate at another sidewall location on the same chip or another chip.

公开(公告)号：US20220352121A1

公开(公告)日：2022-11-03

申请号：US17858031

申请日：2022-07-05

申请人： Intel Corporation

发明人： Debendra MALLIK ,  Digvijay A. RAORANE ,  Ravindranath Vithal MAHAJAN ,  Mitul Bharat MODI

IPC分类号： H01L25/065 ,  H01L21/768 ,  H01L21/822 ,  H01L23/31 ,  H01L23/42 ,  H01L23/48 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

摘要： Semiconductor packages including passive support wafers, and methods of fabricating such semiconductor packages, are described. In an example, a semiconductor package includes a passive support wafer mounted on several active dies. The active dies may be attached to an active die wafer, and the passive support wafer may include a monolithic form to stabilize the active dies and active die wafer during processing and use. Furthermore, the passive support wafer may include a monolith of non-polymeric material to transfer and uniformly distribute heat generated by the active dies.

公开(公告)号：US20220230972A1

公开(公告)日：2022-07-21

申请号：US17714944

申请日：2022-04-06

申请人： Intel Corporation

发明人： Digvijay A. RAORANE ,  Ian En Yoon CHIN ,  Daniel N. SOBIESKI

IPC分类号： H01L23/00 ,  H01L21/50 ,  H01L23/498

摘要： Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.

公开(公告)号：US20200083180A1

公开(公告)日：2020-03-12

申请号：US16468266

申请日：2016-12-31

申请人： INTEL CORPORATION

发明人： Debendra MALLIK ,  Digvijay A. RAORANE

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/16 ,  H01L25/065 ,  H01L25/16 ,  H01L25/00

摘要： An electronic package technology is disclosed. A first active die can be mountable to and electrically coupleable to a package substrate. A second active die can be disposed on a top side of the first active die, the second active die being electrically coupleable to one or both of the first active die and the package substrate. At least one open space can be available on the top side of the first active die. At least a portion of a stiffener can substantially fill the at least one open space available on the top side of the first active die.

公开(公告)号：US20160268213A1

公开(公告)日：2016-09-15

申请号：US14642316

申请日：2015-03-09

申请人： INTEL CORPORATION

发明人： Hongjin JIANG ,  Robert STARKSTON ,  Digvijay A. RAORANE ,  Keith D. JONES ,  Ashish DHALL ,  Omkar G. KARHADE ,  Kedar DHANE ,  Suriyakala RAMALINGAM ,  Li-Sheng WENG ,  Robert F. CHENEY ,  Patrick N. STOVER

IPC分类号： H01L23/552 ,  H01L23/00

CPC分类号： H01L23/552 ,  H01L23/16 ,  H01L23/49805 ,  H01L23/5383 ,  H01L23/562 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/32155 ,  H01L2224/73204 ,  H01L2224/83851 ,  H01L2924/014

摘要： An apparatus including a package including a die and a package substrate, the package substrate including a conductor; and a stiffener body electrically coupled to the conductor of the package substrate. An apparatus including a package including a die and a package substrate; a stiffener body coupled to the package substrate; and an electrically conductive path between the stiffener body and the package substrate. A method including electrically coupling a stiffener body to a conductor of a package substrate.

摘要翻译： 一种包括包括管芯和封装基板的封装的装置，所述封装基板包括导体; 以及电耦合到封装衬底的导体的加强体。 一种包括包括管芯和封装衬底的封装的设备; 耦合到所述封装衬底的加强体; 以及在所述加强体和所述封装基板之间的导电路径。 一种包括将加强体电连接到封装基板的导体的方法。

公开(公告)号：US20230197574A1

公开(公告)日：2023-06-22

申请号：US18111329

申请日：2023-02-17

申请人： Intel Corporation

发明人： Aditya S. VAIDYA ,  Ravindranath V. MAHAJAN ,  Digvijay A. RAORANE ,  Paul R. START

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16 ,  H01L23/538 ,  H01L25/065

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/5385 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/09 ,  H01L24/83 ,  H01L25/16 ,  H01L25/0655 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16237

摘要： An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.