公开(公告)号：US09690353B2

公开(公告)日：2017-06-27

申请号：US13799524

申请日：2013-03-13

Applicant: Intel Corporation

Inventor： Douglas Moran ,  Achmed Rumi Zahir ,  William Knolla ,  Hartej Singh ,  Vasudev Vasu Bibikar ,  Sanjeev Jahagirdar ,  Michael Klinglesmith ,  Irwin Vaz ,  Varghese George

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a processor includes at least one functional block and a central power controller. The at least one functional block may include at least one block component and block power logic. The block power logic may be to: receive a first request to initiate a first reduced power mode in the at least one functional block, and in response to the first request, send a notification signal to a central power controller. The central power controller may be to, in response to the notification signal: store a first state of the at least one functional block, and initiate the first reduced power mode in the at least one functional block. Other embodiments are described and claimed.