公开(公告)号：US11190335B2

公开(公告)日：2021-11-30

申请号：US15878348

申请日：2018-01-23

Applicant: Intel Corporation

Inventor： Boon Hong Oh ,  Ivan Fu Sun Teh ,  Chee Seng Tan

IPC: H04L7/06 ,  H04L29/06 ,  H04L7/00 ,  H04L7/04

Abstract: A method for performing pattern detection and alignment on a programmable logic device is disclosed. A word aligner unit, implemented by a hard intellectual property block, is configured to detect a plurality of control characters by recognizing a proper subset of bits that are common among the plurality of control characters. It is determined whether a predetermined number of consecutive control characters has been detected in a frame of data. A boundary location associated with a detected predetermined number of consecutive control characters from the word aligner unit is identified. The frame of data is aligned in response to the boundary location associated with the detected predetermined number of consecutive control characters.

公开(公告)号：US20190280850A1

公开(公告)日：2019-09-12

申请号：US16424071

申请日：2019-05-28

Applicant: Intel Corporation

Inventor： Chee Seng Tan ,  Boon Hong Oh ,  Ivan Fu Sun Teh

IPC: H04L7/00 ,  H04L7/04

Abstract: A receiver circuit includes a transition density detector circuit that generates a transition density signal based on a comparison between a transition density of data words to a transition density threshold. The receiver circuit also includes a bit shift and pattern detector circuit that bit shifts one of the data words to generate bit shifted data in response to the transition density signal indicating that the transition density of the data words has reached the transition density threshold. The bit shift and pattern detector circuit counts a number of bits shifts performed on the bit shifted data to locate a synchronization character. The receiver circuit also includes a word alignment circuit that bit shifts the data words by the number of bits shifts to generate word aligned data.