公开(公告)号：US20180067731A1

公开(公告)日：2018-03-08

申请号：US15813021

申请日：2017-11-14

Applicant: Intel Corporation

Inventor： POLYCHRONIS XEKALAKIS ,  JASON M. AGRON

IPC: G06F9/45 ,  G06F9/30 ,  G06F9/455 ,  G06F9/44 ,  G06F9/38

CPC classification number: G06F8/41 ,  G06F8/52 ,  G06F9/30054 ,  G06F9/30145 ,  G06F9/30174 ,  G06F9/30185 ,  G06F9/3806 ,  G06F9/4484 ,  G06F9/455 ,  G06F9/4552

Abstract: An apparatus and method for a dual return stack buffer (RSB) for use in binary translation systems. For example, one embodiment of a processor comprises: a dual return stack buffer (DRSB) comprising a native RSB and an extended RSB (XRSB), the dual RSB to be used within a binary translation execution environment in which guest call-return instruction sequences are translated to native call-return instruction sequences to be executed directly by the processor; the native RSB to store native return addresses associated with the native call-return instruction sequences; and the XRSB to store emulated return addresses associated with the guest call-return instruction sequences, wherein each native return address stored in the RSB is associated with an emulated return address stored in the XRSB.