公开(公告)号：US20180004522A1

公开(公告)日：2018-01-04

申请号：US15201218

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： VIKASH AGARWAL ,  CHRISTOPHER D. BRYANT ,  JONATHAN D. COMBS ,  STEPHEN J. ROBINSON

IPC: G06F9/30

CPC classification number: G06F9/30043 ,  G06F9/3016 ,  G06F9/3834

Abstract: Apparatuses, methods, and systems relating to memory disambiguation are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, an execution unit to execute the decoded instruction, a retirement unit to retire an executed instruction in program order, and a memory disambiguation circuit to allocate an entry in a memory disambiguation table for a first load instruction that is to be flushed for a memory ordering violation, the entry comprising a counter value and an instruction pointer for the first load instruction.