公开(公告)号：US20160170888A1

公开(公告)日：2016-06-16

申请号：US14566390

申请日：2014-12-10

Applicant: INTEL CORPORATION

Inventor： CHRISTOPHER D. BRYANT ,  STEPHEN J. ROBINSON

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0857 ,  G06F9/48 ,  G06F12/0802 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/281 ,  G06F2212/608 ,  G06F2212/65

Abstract: A first operation associated with a request for a page miss handler may be identified. A second operation associated with a current execution of the page miss handler may also be identified. An age of the first operation and an age of the second operation may be determined. The page miss handler may be interrupted based on the age of the first operation and the age of the second operation by stopping the current execution of the page miss handler for the second operation and starting execution of the page miss handler for the first operation.

Abstract translation: 可以识别与页面未命中处理程序的请求相关联的第一操作。 还可以识别与页面未命中处理程序的当前执行相关联的第二操作。 可以确定第一次手术的年龄和第二次手术的年龄。 可以基于第一操作的年龄和第二操作的年龄来中断页面未命中处理程序，通过停止用于第二操作的页面未命中处理程序的当前执行，并且开始执行第一操作的页面未命中处理程序。

公开(公告)号：US20180004522A1

公开(公告)日：2018-01-04

申请号：US15201218

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： VIKASH AGARWAL ,  CHRISTOPHER D. BRYANT ,  JONATHAN D. COMBS ,  STEPHEN J. ROBINSON

IPC: G06F9/30

CPC classification number: G06F9/30043 ,  G06F9/3016 ,  G06F9/3834

Abstract: Apparatuses, methods, and systems relating to memory disambiguation are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, an execution unit to execute the decoded instruction, a retirement unit to retire an executed instruction in program order, and a memory disambiguation circuit to allocate an entry in a memory disambiguation table for a first load instruction that is to be flushed for a memory ordering violation, the entry comprising a counter value and an instruction pointer for the first load instruction.

公开(公告)号：US20160170820A1

公开(公告)日：2016-06-16

申请号：US14566374

申请日：2014-12-10

Applicant: Intel Corporation

Inventor： BEEMAN C. STRONG ,  STEPHEN J. ROBINSON ,  JASON W. BRANDT ,  PETER LACHNER

IPC: G06F11/07 ,  G06F11/34

CPC classification number: G06F11/3466 ,  G06F9/30 ,  G06F11/3636

Abstract: A processing device implementing tracking of deferred data packets in a debug trace architecture is disclosed. The processing device is to determine an order number corresponding to an order in which an instruction was executed relative to other executed instructions that correspond to an instruction type within a sequence of executed instructions, identify a first data packet corresponding to a first packet type and sequentially ordered, according to the order number, with respect to data packets of the first packet type within a data trace log, identify a second data packet corresponding to a second packet type and sequentially ordered, according to the order number, with respect to data packets of the second packet type within the data trace log, and map the identified first and second data packets to the instruction, wherein at least one of the first or second data packets was generated post-retirement of the instruction.

Abstract translation: 公开了一种在调试跟踪架构中实现跟踪延迟数据分组的处理设备。 处理装置是确定与执行指令相对应的顺序相对于执行指令序列中的指令类型的其他执行指令的顺序，识别对应于第一分组类型的第一数据分组，并依次 根据订单编号对数据跟踪日志中的第一分组类型的数据分组进行排序，识别与第二分组类型对应的第二数据分组，并根据订单号对数据分组进行顺序排序 的数据跟踪日志中的第二分组类型，并将所识别的第一和第二数据分组映射到指令，其中在指令的退休之后生成第一或第二数据分组中的至少一个。