公开(公告)号：US20190045028A1

公开(公告)日：2019-02-07

申请号：US16021827

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Piotr Wysocki ,  Maciej Andrzej Koprowski ,  Grzegorz Jereczek

IPC: H04L29/08 ,  H04L12/24 ,  H04L12/26

Abstract: Technologies for end-to-end quality of service for I/O operations include a compute device in an I/O path. The compute device receives from another of the compute devices in the I/O path, an I/O request packet. The I/O request packet includes one or more QoS deadline metadata. The QoS deadline metadata is indicative of latency information relating to a currently executing workload relative to a specified QoS. The compute device evaluates the QoS deadline metadata and assigns a priority to the I/O request packet as a function of the evaluated metadata.

公开(公告)号：US10552319B2

公开(公告)日：2020-02-04

申请号：US15995213

申请日：2018-06-01

Applicant: Intel Corporation

Inventor： Grzegorz Jereczek ,  Pawel Lebioda ,  Maciej Maciejewski ,  Pawel Makowski ,  Piotr Pelplinski ,  Jakub Radtke ,  Aleksandra Wisz

IPC: G06F12/00 ,  G06F12/06 ,  G06F9/30 ,  G06F12/0862 ,  G06F13/00 ,  G06F13/28 ,  G11C7/10

Abstract: An embodiment of a semiconductor apparatus may include technology to identify a group of objects based on a common object structure, and allocate the group of objects to two or more memory channels based on interleave set information. Other embodiments are disclosed and claimed.

公开(公告)号：US10715437B2

公开(公告)日：2020-07-14

申请号：US16047445

申请日：2018-07-27

Applicant: Intel Corporation

Inventor： Grzegorz Jereczek ,  Maciej Andrzej Koprowski ,  Piotr Wysocki

IPC: H04L12/741 ,  H04L12/751 ,  H04L29/12 ,  H04L12/851 ,  H04L12/875

Abstract: Examples may include an apparatus having a packet receiver to receive a packet, the packet including a packet header having a deadline and a destination network node. The apparatus includes a routing table including a current latency for a path to the destination network node for the packet. The apparatus further includes a reprioritization component to get the deadline for delivery of the packet to the destination network node, to set a remaining time for the packet to the deadline minus a current time, to subtract the current latency from the remaining time when the packet is to be routed, and to assign the packet to one of a plurality of deadline bins based at least in part on the remaining time, each deadline bin associated with one of a plurality of transmit queues, the plurality of deadline bins arranged in a deadline priority order from a highest priority to a lowest priority. The apparatus also includes a packet transmitter to transmit packets from the plurality of transmit queues, the plurality of transmit queues being accessed in the deadline priority order.

公开(公告)号：US20200007546A1

公开(公告)日：2020-01-02

申请号：US16021816

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Real Valiquette ,  Carl Geoffrion ,  Andre Sylvain ,  Grzegorz Jereczek

IPC: H04L29/06

Abstract: Technologies for updating an access control list (ACL) table while minimizing disruption includes a network device. The network device receives a request to store a rule in the ACL. The rule is associated with a precedence group. A precedence group is indicative of a placement priority of a given rule in the ACL. The network device determines, as a function of the precedence group, a placement for the requested rule in the ACL. The network device stores the rule according to the determined placement in the ACL.

公开(公告)号：US20190042409A1

公开(公告)日：2019-02-07

申请号：US15995213

申请日：2018-06-01

Applicant: Intel Corporation

Inventor： Grzegorz Jereczek ,  Pawel Lebioda ,  Maciej Maciejewski ,  Pawel Makowski ,  Piotr Pelplinski ,  Jakub Radtke ,  Aleksandra Wisz

IPC: G06F12/06 ,  G06F12/0862 ,  G06F9/30

Abstract: An embodiment of a semiconductor apparatus may include technology to identify a group of objects based on a common object structure, and allocate the group of objects to two or more memory channels based on interleave set information. Other embodiments are disclosed and claimed.

公开(公告)号：US11483313B2

公开(公告)日：2022-10-25

申请号：US16021816

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Real Valiquette ,  Carl Geoffrion ,  Andre Sylvain ,  Grzegorz Jereczek

IPC: H04L29/06 ,  H04L9/40

Abstract: Technologies for updating an access control list (ACL) table while minimizing disruption includes a network device. The network device receives a request to store a rule in the ACL. The rule is associated with a precedence group. A precedence group is indicative of a placement priority of a given rule in the ACL. The network device determines, as a function of the precedence group, a placement for the requested rule in the ACL. The network device stores the rule according to the determined placement in the ACL.

公开(公告)号：US11469915B2

公开(公告)日：2022-10-11

申请号：US16975928

申请日：2018-06-12

Applicant: INTEL CORPORATION

Inventor： Grzegorz Jereczek ,  Amruth Gouda Parameshwarappa ,  Christopher Edmiston ,  Maciej Andrzej Koprowski

IPC: H04L12/18 ,  H04L49/00

Abstract: Technologies include a network switch configured to perform packet replication. The network switch includes a network communicator, an entity manager, and a tag manager. The network communicator is to receive a data packet, and the entity manger is to identify an entity associated with the data packet and determine a tag associated with the entity. Additionally, the tag manager is to determine a packet replication configuration associated with the tag, and perform one or more per-port forwarding actions based on the packet replication configuration. The packet replication configuration includes one or more destination ports to be masked and a number of copies to be replicated to be sent out on of at least one destination port.

公开(公告)号：US11025745B2

公开(公告)日：2021-06-01

申请号：US16021827

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Piotr Wysocki ,  Maciej Andrzej Koprowski ,  Grzegorz Jereczek

IPC: H04L29/08 ,  H04L12/24 ,  H04L12/26

Abstract: Technologies for end-to-end quality of service for I/O operations include a compute device in an I/O path. The compute device receives from another of the compute devices in the I/O path, an I/O request packet. The I/O request packet includes one or more QoS deadline metadata. The QoS deadline metadata is indicative of latency information relating to a currently executing workload relative to a specified QoS. The compute device evaluates the QoS deadline metadata and assigns a priority to the I/O request packet as a function of the evaluated metadata.

公开(公告)号：US10691506B2

公开(公告)日：2020-06-23

申请号：US16236162

申请日：2018-12-28

Applicant: INTEL CORPORATION

Inventor： Grzegorz Jereczek ,  Jakub Radtke ,  Pawel Makowski ,  Maciej Maciejewski ,  Pawel Lebioda ,  Piotr Pelplinski ,  Aleksandra Wisz

IPC: G06F16/23 ,  G06F9/52 ,  G06F9/50 ,  H04L9/06 ,  G06F16/907 ,  G06F16/182

Abstract: Systems and methods for managing locks in a data acquisition system with a distributed data storage are disclosed. In embodiments, a storage node of a data acquisition system with a plurality of storage nodes receives a request for an unprocessed event, where portions of the event data are stored across the plurality of storage nodes. One node of the plurality of nodes holds the lock value for the event. The node receiving the request searches for an event where it stores the lock value that is unlocked. If none is found, the node receiving the request forwards the request to a second node, which repeats the search.