公开(公告)号：US20230198548A1

公开(公告)日：2023-06-22

申请号：US17559989

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： James David Guilford ,  Vinodh Gopal ,  Daniel Frederick Cutter ,  Kirk Yap

IPC: H03M7/30 ,  H03M7/40

CPC classification number: H03M7/3084 ,  H03M7/40

Abstract: Apparatus and method for detecting a constant data block are described herein. An apparatus embodiment includes compression circuitry to perform compression operations on a memory block; constant detection circuitry to, concurrently with performance of the compression operations on the memory block, determine that the memory block is a constant data block comprised of only repeat instances of a constant value; and controller circuitry to associate a first indication with the memory block based on the determination, the first indication usable for controlling whether to abort the compression operations or whether to discard a compressed memory block generated from the compression operations.

公开(公告)号：US20230098331A1

公开(公告)日：2023-03-30

申请号：US17485384

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James David Guilford ,  Otto Bruggeman

IPC: G06F16/245

Abstract: Embodiments of apparatuses, methods, and systems for a complex filter hardware accelerator are disclosed. In an embodiment, an apparatus includes a plurality of set membership definition units and set lookup request generator hardware. Each set membership definition unit has a memory to store a definition indicator per input value. Each definition indicator is to indicate whether a corresponding input value corresponds to membership in a set. Each input value is to have a fixed width, in bits, less than an element width, in bits, of each set member. The set lookup request generator hardware is to access one of the plurality of set membership definition units. Which one of the plurality of set membership definition units to be accessed is to be determined based on an offset value. The offset value is to have an offset width, in bits, equal to the element width minus the fixed width.

公开(公告)号：US20220414014A1

公开(公告)日：2022-12-29

申请号：US17304656

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： James David Guilford ,  Vinodh Gopal ,  Daniel Frederick Cutter

IPC: G06F12/0875 ,  G06F12/126 ,  G06F12/0891 ,  G06F12/02 ,  G06F12/06

Abstract: An integrated circuit includes a compression accelerator to process a request from software to compress source data into an output file. The compression accelerator includes early-abort circuitry to provide for early abort of compression operations. In particular, the compression accelerator uses a predetermined sample size to compute an estimated size for a portion of the output file. The sample size specifies how much of the source data is to be analyzed before computing the estimated size. The compression accelerator also determines whether the estimated size reflects an acceptable amount of compression, based on a predetermined early-abort threshold. The compression accelerator aborts the request if the estimated size does not reflect the acceptable amount of compression. The compression accelerator may complete the request if the estimated size reflects the acceptable amount of compression. Other embodiments are described and claimed.