公开(公告)号：US09330022B2

公开(公告)日：2016-05-03

申请号：US13926564

申请日：2013-06-25

Applicant: Intel Corporation

Inventor： James E Phillips ,  Wing Shek Wong ,  Charles Vitu

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/32

CPC classification number: G06F12/1036 ,  G06F9/3001 ,  G06F9/32

Abstract: In an embodiment, a processor includes a plurality of cores. Each core includes conversion power logic to receive an instruction including an untranslated memory address, determine whether a code segment (CS) base address is equal to zero, and in response to a determination that the CS base address is equal to zero, execute the instruction using the untranslated memory address. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个核。 每个核心包括用于接收包括非翻译存储器地址的指令的转换功率逻辑，确定代码段（CS）基地址是否等于零，并且响应于CS基地址等于零的确定，执行指令 使用非翻译的内存地址。 描述和要求保护其他实施例。