公开(公告)号：US12039329B2

公开(公告)日：2024-07-16

申请号：US17134108

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Wing Shek Wong ,  Vikash Agarwal ,  Charles Vitu ,  Mihir Shah

IPC: G06F9/24 ,  G06F9/22 ,  G06F9/30

CPC classification number: G06F9/223 ,  G06F9/30145

Abstract: Systems, methods, and apparatuses relating to circuitry to implement dynamic two-pass execution of a partial flag updating instruction in a processor are described. In one embodiment, a hardware processor core includes a decoder circuit to decode instructions into a set of one or more micro-operations, an execution circuit to execute the micro-operations decoded for the instructions, a data register to store data, a flag register to store a plurality of flags, and a reservation station circuit coupled between the decoder circuit and the execution circuit, the reservation station circuit to, in response to an indicator bit set to a multiple pass mode for a single micro-operation in a reservation station entry, perform a first dispatch of the single micro-operation to the execution circuit, when a source data operand in the data register is ready for execution and a source flag operand in the flag register is not ready for execution, to generate a data resultant, and a second dispatch of the single micro-operation to the execution circuit when both the source data operand in the data register and the source flag operand in the flag register are ready for execution to generate a flag resultant based on one or more of the plurality of flags in the flag register.

公开(公告)号：US09330022B2

公开(公告)日：2016-05-03

申请号：US13926564

申请日：2013-06-25

Applicant: Intel Corporation

Inventor： James E Phillips ,  Wing Shek Wong ,  Charles Vitu

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/32

CPC classification number: G06F12/1036 ,  G06F9/3001 ,  G06F9/32

Abstract: In an embodiment, a processor includes a plurality of cores. Each core includes conversion power logic to receive an instruction including an untranslated memory address, determine whether a code segment (CS) base address is equal to zero, and in response to a determination that the CS base address is equal to zero, execute the instruction using the untranslated memory address. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个核。 每个核心包括用于接收包括非翻译存储器地址的指令的转换功率逻辑，确定代码段（CS）基地址是否等于零，并且响应于CS基地址等于零的确定，执行指令 使用非翻译的内存地址。 描述和要求保护其他实施例。