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公开(公告)号：US10853078B2
公开(公告)日：2020-12-01
申请号：US16231313
申请日：2018-12-21
Applicant: Intel Corporation
Inventor： Vineeth Mekkat , Mark Dechene , Zhongying Zhang , John Faistl , Janghaeng Lee , Hou-Jen Ko , Sebastian Winkel , Oleg Margulis
Abstract: A processor includes a store buffer to store store instructions to be processed to store data in main memory, a load buffer to store load instructions to be processed to load data from main memory, and a loop invariant code motion (LICM) protection structure coupled to the store buffer and the load buffer. The LPT tracks information to compare an address of a store or snoop microoperation with entries in the LICM and re-loads a load microoperation of a matching entry.
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公开(公告)号：US10235177B2
公开(公告)日：2019-03-19
申请号：US15201403
申请日：2016-07-02
Applicant: Intel Corporation
Inventor： Vineeth Mekkat , Janghaeng Lee , Youfeng Wu
Abstract: In an example, an apparatus includes a binary translator (BT) including circuitry to: analyze a code block; determine that an architectural register mapped to a physical register in the physical register file is available for early reclamation; and insert a reclamation hint into the code block. In another example, a processor reclaims the physical register based at least in part on the reclamation hint.
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公开(公告)号：US20180004524A1
公开(公告)日：2018-01-04
申请号：US15201403
申请日：2016-07-02
Applicant: Intel Corporation
Inventor： Vineeth Mekkat , Janghaeng Lee , Youfeng Wu
IPC: G06F9/30
CPC classification number: G06F9/30123 , G06F8/41 , G06F9/3016 , G06F9/384
Abstract: In an example, there is disclosed an apparatus, including a binary translator (BT) including circuitry to: analyze a code block; determine that an architectural register mapped to a physical register in the physical register file is available for early reclamation; and insert a reclamation hint into the code block. There is also disclosed a processor to reclaim the physical register based at least in part on the reclamation hint.
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