公开(公告)号：US20180285113A1

公开(公告)日：2018-10-04

申请号：US15475389

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Hou-Jen Ko ,  Girish Venkatasubramanian ,  Jason Agron ,  Tyler Sondag ,  Youfeng Wu

IPC: G06F9/30

CPC classification number: G06F9/30174 ,  G06F9/3016

Abstract: In one example a processor includes a region formation engine to identify a region of code for translation from a guest instruction set architecture to a native instruction set architecture. The processor also includes a binary translator to translate the region of code. The region formation engine is to perform aggressive region formation, which includes forming a region across a boundary of a return instruction. The translated region of code is to prevent a side entry into the translated region of code at a translated return target instruction included in the translated region of code. In more specific examples, performing aggressive region formation includes a region formation grow phase and a region formation cleanup phase. In the grow phase priority may be given to growing complete paths from a call target to a corresponding return. The region formation cleanup phase may comprise eliminating call targets that are not reachable.

公开(公告)号：US10853078B2

公开(公告)日：2020-12-01

申请号：US16231313

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Mark Dechene ,  Zhongying Zhang ,  John Faistl ,  Janghaeng Lee ,  Hou-Jen Ko ,  Sebastian Winkel ,  Oleg Margulis

IPC: G06F9/312 ,  G06F9/40 ,  G06F9/44 ,  G06F9/38 ,  G06F9/30 ,  G06F8/41

Abstract: A processor includes a store buffer to store store instructions to be processed to store data in main memory, a load buffer to store load instructions to be processed to load data from main memory, and a loop invariant code motion (LICM) protection structure coupled to the store buffer and the load buffer. The LPT tracks information to compare an address of a store or snoop microoperation with entries in the LICM and re-loads a load microoperation of a matching entry.

公开(公告)号：US10191745B2

公开(公告)日：2019-01-29

申请号：US15475389

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Hou-Jen Ko ,  Girish Venkatasubramanian ,  Jason Agron ,  Tyler Sondag ,  Youfeng Wu

IPC: G06F9/45 ,  G06F9/30

Abstract: In one example a processor includes a region formation engine to identify a region of code for translation from a guest instruction set architecture to a native instruction set architecture. The processor also includes a binary translator to translate the region of code. The region formation engine is to perform aggressive region formation, which includes forming a region across a boundary of a return instruction. The translated region of code is to prevent a side entry into the translated region of code at a translated return target instruction included in the translated region of code. In more specific examples, performing aggressive region formation includes a region formation grow phase and a region formation cleanup phase. In the grow phase priority may be given to growing complete paths from a call target to a corresponding return. The region formation cleanup phase may comprise eliminating call targets that are not reachable.