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公开(公告)号：US20160344379A9
公开(公告)日：2016-11-24
申请号：US14929154
申请日：2015-10-30
Applicant: INTEL CORPORATION
Inventor： Mark NEIDENGARD , Vaughn GROSSNICKLE , Nasser KURD , Jeffrey KRIEGER
CPC classification number: H03K5/1565 , H03K3/0315
Abstract: Described herein are apparatus, method, and system for re-synthesizing a clock signal. The apparatus comprises: a first logic unit to detect a rising edge of an input clock signal and for generating a rising edge of an output clock signal based on the detected rising edge of the input clock signal, the input clock signal having a non-50% duty cycle and a first period; and a second logic unit to compute a falling edge of the output clock signal according to the detected rising edge of the input clock signal, the falling edge of the output clock signal being near half of the first period.
Abstract translation: 这里描述了用于重新合成时钟信号的装置，方法和系统。 该装置包括：第一逻辑单元，用于检测输入时钟信号的上升沿，并且用于基于检测到的输入时钟信号的上升沿产生输出时钟信号的上升沿，所述输入时钟信号具有非50 占空比的百分之一和第一期; 以及第二逻辑单元，用于根据检测到的输入时钟信号的上升沿计算输出时钟信号的下降沿，输出时钟信号的下降沿接近第一周期的一半。
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公开(公告)号：US20160056807A1
公开(公告)日：2016-02-25
申请号：US14929154
申请日：2015-10-30
Applicant: INTEL CORPORATION
Inventor： Mark NEIDENGARD , Vaughn GROSSNICKLE , Nasser KURD , Jeffrey KRIEGER
CPC classification number: H03K5/1565 , H03K3/0315
Abstract: Described herein are apparatus, method, and system for re-synthesizing a clock signal. The apparatus comprises: a first logic unit to detect a rising edge of an input clock signal and for generating a rising edge of an output clock signal based on the detected rising edge of the input clock signal, the input clock signal having a non-50% duty cycle and a first period; and a second logic unit to compute a falling edge of the output clock signal according to the detected rising edge of the input clock signal, the falling edge of the output clock signal being near half of the first period.
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公开(公告)号：US20210153351A1
公开(公告)日：2021-05-20
申请号：US17127829
申请日：2020-12-18
Applicant: Intel Corporation
Inventor： Xiang LI , George VERGIS , Jeffrey KRIEGER
Abstract: Connectors with a hybrid pitch are described. In one example, a connector to couple a card or module to a motherboard includes connector housing and a plurality of pins. The plurality of pins include alternating signal and ground pins. Each of the plurality of pins includes a card or module-facing end to couple with the card or module and a lead to couple with a through hole in the motherboard. A first pitch between leads of a pin and a first adjacent pin is different than a second pitch between leads of the pin and a second adjacent pin.
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