公开(公告)号：US10884476B2

公开(公告)日：2021-01-05

申请号：US16290310

申请日：2019-03-01

申请人： Intel Corporation

发明人： Vinu K. Elias ,  Sundar Ramani ,  Arvind S. Tomar ,  Jianjun Liu

IPC分类号： G06F1/32 ,  G06F1/3212 ,  H03K19/0185 ,  G06F1/3234 ,  G11C7/10

摘要： In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state. Other embodiments are described and claimed.

公开(公告)号：US20190196568A1

公开(公告)日：2019-06-27

申请号：US16290310

申请日：2019-03-01

申请人： Intel Corporation

发明人： Vinu K. Elias ,  Sundar Ramani ,  Arvind S. Tomar ,  Jianjun Liu

IPC分类号： G06F1/3212 ,  H03K19/0185 ,  G06F1/3234

CPC分类号： G06F1/3212 ,  G06F1/3234 ,  G11C7/1057 ,  G11C7/1084 ,  G11C2207/105 ,  H03K19/018585 ,  H03K19/018592

摘要： In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state. Other embodiments are described and claimed.

公开(公告)号：US10241556B2

公开(公告)日：2019-03-26

申请号：US15025575

申请日：2013-11-27

申请人： Intel Corporation

发明人： Vinu K. Elias ,  Sundar Ramani ,  Arvind S. Tomar ,  Jianjun Liu

IPC分类号： G06F1/32 ,  G06F1/3212 ,  H03K19/0185 ,  G06F1/3234 ,  G11C7/10

摘要： In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state. Other embodiments are described and claimed.