公开(公告)号：US10963038B2

公开(公告)日：2021-03-30

申请号：US16252816

申请日：2019-01-21

Applicant: Intel Corporation

Inventor： Sundar Ramani ,  Arvind Raman ,  Arvind Mandhani ,  Ashish V. Choubal ,  Kalyan Muthukumar ,  Ajaya V. Durg ,  Samudyatha Chakki

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3203 ,  G06F1/3296 ,  G06F12/0815 ,  G06F12/0804 ,  G06F12/084 ,  G06F1/324 ,  G06F1/3234 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/128 ,  G06F12/0811 ,  G06F12/12

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

公开(公告)号：US10241556B2

公开(公告)日：2019-03-26

申请号：US15025575

申请日：2013-11-27

Applicant: Intel Corporation

Inventor： Vinu K. Elias ,  Sundar Ramani ,  Arvind S. Tomar ,  Jianjun Liu

IPC: G06F1/32 ,  G06F1/3212 ,  H03K19/0185 ,  G06F1/3234 ,  G11C7/10

Abstract: In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state. Other embodiments are described and claimed.

公开(公告)号：US10198065B2

公开(公告)日：2019-02-05

申请号：US15494625

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Sundar Ramani ,  Arvind Raman ,  Arvind Mandhani ,  Ashish V. Choubal ,  Kalyan Muthukumar ,  Ajaya V. Durg ,  Samudyatha Chakki

IPC: G06F1/32 ,  G06F12/0815 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/128 ,  G06F12/0811

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

公开(公告)号：US20170228014A1

公开(公告)日：2017-08-10

申请号：US15494625

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Sundar Ramani ,  Arvind Raman ,  Arvind Mandhani ,  Ashish V. Choubal ,  Kalyan Muthukumar ,  Ajaya V. Durg ,  Samudyatha Chakki

IPC: G06F1/32 ,  G06F12/128 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0808

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/12 ,  G06F12/128 ,  G06F2212/1028 ,  G06F2212/314 ,  G06F2212/621 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

公开(公告)号：US20190196568A1

公开(公告)日：2019-06-27

申请号：US16290310

申请日：2019-03-01

Applicant: Intel Corporation

Inventor： Vinu K. Elias ,  Sundar Ramani ,  Arvind S. Tomar ,  Jianjun Liu

IPC: G06F1/3212 ,  H03K19/0185 ,  G06F1/3234

CPC classification number: G06F1/3212 ,  G06F1/3234 ,  G11C7/1057 ,  G11C7/1084 ,  G11C2207/105 ,  H03K19/018585 ,  H03K19/018592

Abstract: In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state. Other embodiments are described and claimed.

公开(公告)号：US20190155370A1

公开(公告)日：2019-05-23

申请号：US16252816

申请日：2019-01-21

Applicant: Intel Corporation

Inventor： Sundar Ramani ,  Arvind Raman ,  Arvind Mandhani ,  Ashish V. Choubal ,  Kalyan Muthukumar ,  Ajaya V. Durg ,  Samudyatha Chakki

IPC: G06F1/3287 ,  G06F1/3296 ,  G06F1/3203 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/128 ,  G06F12/0831 ,  G06F12/0808 ,  G06F1/324 ,  G06F1/3234 ,  G06F12/0815

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

公开(公告)号：US09665153B2

公开(公告)日：2017-05-30

申请号：US14221696

申请日：2014-03-21

Applicant: Intel Corporation

Inventor： Sundar Ramani ,  Arvind Raman ,  Arvind Mandhani ,  Ashish V. Choubal ,  Kalyan Muthukumar ,  Ajaya V. Durg ,  Samudyatha Chakki

IPC: G06F1/32 ,  G06F12/0815 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0811

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/128 ,  G06F2212/1028 ,  G06F2212/314 ,  G06F2212/621 ,  G06F2212/69 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

公开(公告)号：US11567555B2

公开(公告)日：2023-01-31

申请号：US16557657

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Jason Seung-Min Kim ,  Sundar Ramani ,  Yogesh Bansal ,  Nitin N. Garegrat ,  Olivia K. Wu ,  Mayank Kaushik ,  Mrinal Iyer ,  Tom Schebye ,  Andrew Yang

IPC: G06F1/324 ,  G06F1/08 ,  G06F1/28 ,  G06F1/12 ,  G06F9/30 ,  G06F9/28 ,  G06N3/08

Abstract: Embodiments include an apparatus comprising an execution unit coupled to a memory, a microcode controller, and a hardware controller. The microcode controller is to identify a global power and performance hint in an instruction stream that includes first and second instruction phases to be executed in parallel, identify a local hint based on synchronization dependence in the first instruction phase, and use the first local hint to balance power consumption between the execution unit and the memory during parallel executions of the first and second instruction phases. The hardware controller is to use the global hint to determine an appropriate voltage level of a compute voltage and a frequency of a compute clock signal for the execution unit during the parallel executions of the first and second instruction phases. The first local hint includes a processing rate for the first instruction phase or an indication of the processing rate.

公开(公告)号：US10884476B2

公开(公告)日：2021-01-05

申请号：US16290310

申请日：2019-03-01

Applicant: Intel Corporation

Inventor： Vinu K. Elias ,  Sundar Ramani ,  Arvind S. Tomar ,  Jianjun Liu

IPC: G06F1/32 ,  G06F1/3212 ,  H03K19/0185 ,  G06F1/3234 ,  G11C7/10

Abstract: In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state. Other embodiments are described and claimed.