公开(公告)号：US20240006512A1

公开(公告)日：2024-01-04

申请号：US17853500

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Walter CASPER, IV ,  Sudipto NASKAR ,  Marci Kahiehie Mi Hyon KANG ,  Weimin HAN ,  Vivek THIRTHA ,  Jianqiang LIN

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L29/6656 ,  H01L21/0228 ,  H01L29/0669 ,  H01L29/0847

Abstract: Embodiments disclosed herein include a transistor and methods of making a transistor. In an embodiment, the transistor comprises a channel region and a gate structure over the channel region. In an embodiment, a first spacer is on a first end of the gate structure, and a second spacer is on a second end of the gate structure. In an embodiment, individual ones of the first spacer and the second spacer comprise a first layer with a first dielectric constant, and a second layer with a second dielectric constant that is higher than the first dielectric constant. In an embodiment, the transistor further comprises a source region adjacent to the first spacer, and a drain region adjacent to the second spacer.