公开(公告)号：US20220130962A1

公开(公告)日：2022-04-28

申请号：US17569376

申请日：2022-01-05

Applicant: Intel Corporation

Inventor： Gopinath BHIMARASETTI ,  Walid M. HAFEZ ,  Joodong PARK ,  Weimin HAN ,  Raymond E. COTNER ,  Chia-Hong JAN

IPC: H01L29/36 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

公开(公告)号：US20240006512A1

公开(公告)日：2024-01-04

申请号：US17853500

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Walter CASPER, IV ,  Sudipto NASKAR ,  Marci Kahiehie Mi Hyon KANG ,  Weimin HAN ,  Vivek THIRTHA ,  Jianqiang LIN

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L29/6656 ,  H01L21/0228 ,  H01L29/0669 ,  H01L29/0847

Abstract: Embodiments disclosed herein include a transistor and methods of making a transistor. In an embodiment, the transistor comprises a channel region and a gate structure over the channel region. In an embodiment, a first spacer is on a first end of the gate structure, and a second spacer is on a second end of the gate structure. In an embodiment, individual ones of the first spacer and the second spacer comprise a first layer with a first dielectric constant, and a second layer with a second dielectric constant that is higher than the first dielectric constant. In an embodiment, the transistor further comprises a source region adjacent to the first spacer, and a drain region adjacent to the second spacer.

公开(公告)号：US20230178426A1

公开(公告)日：2023-06-08

申请号：US17541976

申请日：2021-12-03

Applicant: Intel Corporation

Inventor： Tiffany ZINK ,  Shashi VYAS ,  Weimin HAN ,  Sudipto NASKAR ,  Charles H. WALLACE

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76834 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76844 ,  H01L23/5226 ,  H01L21/76877 ,  H01L23/53228

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer over a conductive interconnect line, the ILD layer having a trench therein, the trench exposing a portion of the conductive interconnect line. A dielectric liner layer is along a top surface of the ILD layer and along sidewalls of the trench, the dielectric liner layer having an opening therein, the opening over the portion of the conductive interconnect line. A conductive via structure is in the trench and between portions of the dielectric liner layer along the sidewalls of the trench, the conductive via structure having a portion extending vertically beneath the dielectric liner layer and in contact with the portion of the conductive interconnect line.

公开(公告)号：US20190296114A1

公开(公告)日：2019-09-26

申请号：US16435301

申请日：2019-06-07

Applicant: Intel Corporation

Inventor： Gopinath BHIMARASETTI ,  Walid M. HAFEZ ,  Joodong PARK ,  Weimin HAN ,  Raymond E. COTNER ,  Chia-Hong JAN

IPC: H01L29/36 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.