公开(公告)号：US20210103308A1

公开(公告)日：2021-04-08

申请号：US17100603

申请日：2020-11-20

Applicant: Intel Corporation

Inventor： Xiaosen Liu ,  Harish Krishnamurthy ,  Krishnan Ravichandran ,  Vivek De ,  Scott Chiu ,  Claudia Patricia Barrera Gonzalez ,  Jing Han ,  Rajasekhara Madhusudan Narayana Bhatla

IPC: G05F1/56 ,  G05F1/46 ,  G05F1/67

Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.

公开(公告)号：US11940824B2

公开(公告)日：2024-03-26

申请号：US17100603

申请日：2020-11-20

Applicant: Intel Corporation

Inventor： Xiaosen Liu ,  Harish Krishnamurthy ,  Krishnan Ravichandran ,  Vivek De ,  Scott Chiu ,  Claudia Patricia Barrera Gonzalez ,  Jing Han ,  Rajasekhara Madhusudan Narayana Bhatla

IPC: G05F1/56 ,  G05F1/46 ,  G05F1/67

CPC classification number: G05F1/56 ,  G05F1/462 ,  G05F1/67

Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.

公开(公告)号：US20190317536A1

公开(公告)日：2019-10-17

申请号：US16450873

申请日：2019-06-24

Applicant: Intel Corporation

Inventor： Xiaosen Liu ,  Harish Krishnamurthy ,  Krishnan Ravichandran ,  Vivek De ,  Scott Chiu ,  Claudia Patricia Barrera Gonzalez ,  Jing Han ,  Rajasekhara Madhusudan Narayana Bhatla

IPC: G05F1/56 ,  G05F1/67 ,  G05F1/46

Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.