公开(公告)号：US11940824B2

公开(公告)日：2024-03-26

申请号：US17100603

申请日：2020-11-20

Applicant: Intel Corporation

Inventor： Xiaosen Liu ,  Harish Krishnamurthy ,  Krishnan Ravichandran ,  Vivek De ,  Scott Chiu ,  Claudia Patricia Barrera Gonzalez ,  Jing Han ,  Rajasekhara Madhusudan Narayana Bhatla

IPC: G05F1/56 ,  G05F1/46 ,  G05F1/67

CPC classification number: G05F1/56 ,  G05F1/462 ,  G05F1/67

Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.

公开(公告)号：US20190317536A1

公开(公告)日：2019-10-17

申请号：US16450873

申请日：2019-06-24

Applicant: Intel Corporation

Inventor： Xiaosen Liu ,  Harish Krishnamurthy ,  Krishnan Ravichandran ,  Vivek De ,  Scott Chiu ,  Claudia Patricia Barrera Gonzalez ,  Jing Han ,  Rajasekhara Madhusudan Narayana Bhatla

IPC: G05F1/56 ,  G05F1/67 ,  G05F1/46

Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.

公开(公告)号：US09305613B2

公开(公告)日：2016-04-05

申请号：US14173221

申请日：2014-02-05

Applicant: Intel Corporation

Inventor： Scott Chiu ,  Mohamed Arafa

IPC: G06F12/00 ,  G11C7/10 ,  G06F13/16 ,  G11C5/04 ,  G06F13/00 ,  G06F13/28 ,  G06F1/32

CPC classification number: G11C7/10 ,  G06F1/3275 ,  G06F1/3287 ,  G06F13/1673 ,  G11C5/04 ,  Y02D10/14

Abstract: A memory module can include a data buffer having a data bus interface and a dynamic random access memory (DRAM) coupled to the data buffer. The memory module may also include a switch connected in parallel with the data buffer, wherein the switch can selectively bypass the data buffer. In one example, the memory module also includes a registered buffer having an address bus interface, where the switch may selectively bypass the data buffer based on a program signal obtained from an address bus via the address bus interface.

Abstract translation: 存储器模块可以包括具有数据总线接口的数据缓冲器和耦合到数据缓冲器的动态随机存取存储器（DRAM）。 存储器模块还可以包括与数据缓冲器并联连接的开关，其中开关可以有选择地绕过数据缓冲器。 在一个示例中，存储器模块还包括具有地址总线接口的注册缓冲器，其中交换机可以基于经由地址总线接口从地址总线获得的程序信号选择性地旁路数据缓冲器。

公开(公告)号：US20210103308A1

公开(公告)日：2021-04-08

申请号：US17100603

申请日：2020-11-20

Applicant: Intel Corporation

Inventor： Xiaosen Liu ,  Harish Krishnamurthy ,  Krishnan Ravichandran ,  Vivek De ,  Scott Chiu ,  Claudia Patricia Barrera Gonzalez ,  Jing Han ,  Rajasekhara Madhusudan Narayana Bhatla

IPC: G05F1/56 ,  G05F1/46 ,  G05F1/67

Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.