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公开(公告)号:US20230208689A1
公开(公告)日:2023-06-29
申请号:US17561877
申请日:2021-12-24
Applicant: Intel Corporation
Inventor: Ali Montazeri , Jinyong Lee
IPC: H04L27/144 , H04B1/10
CPC classification number: H04L27/144 , H04B1/10
Abstract: A receiver, including: a sampling circuit configured to convert a received analog signal into a digital signal; a variance determination circuit configured to determine a phase difference variance of the digital signal; and a frequency shift keying (FSK) discrimination circuit configured to discriminate, based on the phase difference variance, whether the received analog signal is an FSK-modulated signal.
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公开(公告)号:US11843460B2
公开(公告)日:2023-12-12
申请号:US17455979
申请日:2021-11-22
Applicant: Intel Corporation
Inventor: Avishay Friedman , Yarden Regev , Jinyong Lee , Assaf Gurevitz
CPC classification number: H04L1/0045 , H04W4/08
Abstract: A Bluetooth receiver is provided. The Bluetooth receiver comprises interface circuitry configured to receive a receive packet. Further, the Bluetooth receiver comprises physical layer processing circuitry configured to demodulate the receive packet into a bit stream representing a sequence of data symbols. Further, the physical layer configured to determine a number of bits in the bit stream having a highest likelihood of being erroneous as weak-bits and determine locations of the identified weak-bits in the bit stream. The Bluetooth receiver further comprises medium access control layer processing circuitry configured to receive the bit stream and information about the determined locations of the identified weak-bits from the physical layer processing circuitry. Further, the medium access control layer is configured to flip one of the weak-bits and a sequential bit in the bit stream in order to generate a modified bit stream, run a respective cyclic redundancy check on the bit stream and the modified bit stream and compare results of the cyclic redundancy checks on the bit stream and on the modified bit stream.
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公开(公告)号:US11553431B2
公开(公告)日:2023-01-10
申请号:US15733329
申请日:2018-08-31
Applicant: Intel Corporation
Inventor: Prasanna Desai , Chen Meng , Yuwei Zhang , Jinyong Lee , Oren Kaidar , Sharon Heruti , Thomas W. Brown , Assaf Gurevitz , Anthony Tsangaropoulos
IPC: H04W52/02 , H04B17/318 , H04B17/345 , H04L1/00 , H04W56/00
Abstract: In one embodiment, an apparatus of a wireless communication device includes control circuitry to cause receiver circuitry of the wireless communication device to switch between an on-mode and an off-mode. The apparatus also includes synchronizing circuitry to: perform a correlation on signals of a packet received by the receiver circuitry when in the on-mode to detect a pattern in the received signals, and cause the control circuitry to hold the receiver circuitry in the on-mode based on detection of the pattern in the received signals. The apparatus further includes demodulation circuitry to process additional signals of the packet received by the receiver circuitry when held in the on-mode.
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公开(公告)号:US20210120496A1
公开(公告)日:2021-04-22
申请号:US15733329
申请日:2018-08-31
Applicant: Intel Corporation
Inventor: Prasanna Desai , Chen Meng , Yuwei Zhang , Jinyong Lee , Oren Kaidar , Sharon Heruti , Thomas W. Brown , Assaf Gurevitz , Anthony Tsangaropoulos
IPC: H04W52/02 , H04B17/318 , H04B17/345 , H04W56/00 , H04L1/00
Abstract: In one embodiment, an apparatus of a wireless communication device includes control circuitry to cause receiver circuitry of the wireless communication device to switch between an on-mode and an off-mode. The apparatus also includes synchronizing circuitry to: perform a correlation on signals of a packet received by the receiver circuitry when in the on-mode to detect a pattern in the received signals, and cause the control circuitry to hold the receiver circuitry in the on-mode based on detection of the pattern in the received signals. The apparatus further includes demodulation circuitry to process additional signals of the packet received by the receiver circuitry when held in the on-mode.
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