公开(公告)号：US20190044892A1

公开(公告)日：2019-02-07

申请号：US16144146

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： John Mangan ,  Niall D. McDonnell ,  Harry Van Haaren ,  Bruce Richardson ,  Ciara Loftus

IPC: H04L12/883 ,  H04L12/935 ,  H04L12/931 ,  G06F9/455

Abstract: Technologies for using a hardware queue manager as a virtual guest to host networking interface include a compute node configured to receive a pointer corresponding to each of one or more available receive buffers from a guest processor core of at least one processor of the compute node that has been allocated to a virtual guest managed by the compute node. The compute node is further configured to enqueue the received pointer of each of the one or more available receive buffers into an available buffer queue and facilitate access to the available receive buffers to at least a portion of a plurality of virtual switch processor cores. Each of the virtual switch processor cores comprises another processor core of the plurality of processor cores that has been allocated to a virtual switch of the compute node. Other embodiments are described herein.

公开(公告)号：US20220286399A1

公开(公告)日：2022-09-08

申请号：US17637416

申请日：2020-09-11

Applicant: Intel Corporation

Inventor： Niall McDonnell ,  Gage Eads ,  Mrittika Ganguli ,  Chetan Hiremath ,  John Mangan ,  Stephen Palermo ,  Bruce Richardson ,  Edwin Verplanke ,  Praveen Mosur ,  Bradley Chaddick ,  Abhishek Khade ,  Abhirupa Layek ,  Sarita Maini ,  Rahul Shah ,  Shrikant Shah ,  William Burroughs ,  David Sonnier

IPC: H04L47/125 ,  H04L47/625 ,  H04L47/62 ,  H04L47/6275

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for hardware queue scheduling for multi-core computing environments. An example apparatus includes a first core and a second core of a processor, and circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet, assign the identifier in the queue to a first core of the processor, and in response to an execution of an operation on the data packet with the first core, provide the identifier to the second core to cause the second core to distribute the data packet.

公开(公告)号：US11489791B2

公开(公告)日：2022-11-01

申请号：US16177262

申请日：2018-10-31

Applicant: Intel Corporation

Inventor： Niall D. McDonnell ,  Bruce Richardson ,  John Mangan ,  Harry Van Haaren ,  Ciara Loftus ,  Brian A. Keating

IPC: G06F13/10 ,  H04L49/00 ,  G06F9/54 ,  H04L49/9005

Abstract: Examples include a method of switching a packet by a virtual switch by receiving a system call to transmit a packet from a first application running in a first container on a first core, determining a destination for the packet, obtaining a buffer in an application memory space of the destination, copying the packet to the destination application memory space, and writing an entry for the packet to a queue assigned to the destination, the destination queue being in a queue manager. The packet may then be obtained by an entity at the destination.