公开(公告)号：US11637687B2

公开(公告)日：2023-04-25

申请号：US16723743

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Ned Smith ,  Francesc Guim Bernat ,  Sanjay Bakshi ,  Paul O'Neill ,  Ben McCahill ,  Brian A. Keating ,  Adrian Hoban ,  Kapil Sood ,  Mona Vij ,  Nilesh Jain ,  Rajesh Poornachandran ,  Trevor Cooper ,  Kshitij A. Doshi ,  Marcin Spoczynski

IPC: H04L29/06 ,  H04L9/00 ,  G06F16/28 ,  H04L9/06

Abstract: Methods, apparatus, systems and articles of manufacture to determine provenance for data supply chains are disclosed. Example instructions cause a machine to at least, in response to data being generated, generate a local data object and object metadata corresponding to the data; hash the local data object; generate a hash of a label of the local data object; generate a hierarchical data structure for the data including the hash of the local data object and the hash of the label of the local data object; generate a data supply chain object including the hierarchical data structure; and transmit the data and the data supply chain object to a device that requested access to the data.

公开(公告)号：US11489791B2

公开(公告)日：2022-11-01

申请号：US16177262

申请日：2018-10-31

Applicant: Intel Corporation

Inventor： Niall D. McDonnell ,  Bruce Richardson ,  John Mangan ,  Harry Van Haaren ,  Ciara Loftus ,  Brian A. Keating

IPC: G06F13/10 ,  H04L49/00 ,  G06F9/54 ,  H04L49/9005

Abstract: Examples include a method of switching a packet by a virtual switch by receiving a system call to transmit a packet from a first application running in a first container on a first core, determining a destination for the packet, obtaining a buffer in an application memory space of the destination, copying the packet to the destination application memory space, and writing an entry for the packet to a queue assigned to the destination, the destination queue being in a queue manager. The packet may then be obtained by an entity at the destination.

公开(公告)号：US11983131B2

公开(公告)日：2024-05-14

申请号：US17134361

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Patrick G. Kutch ,  Andrey Chilikin ,  Niall D. McDonnell ,  Brian A. Keating ,  Naveen Lakkakula ,  Ilango S. Ganga ,  Venkidesh Krishna Iyer ,  Patrick Fleming ,  Lokpraveen Mosur

IPC: G06F13/40 ,  G06F3/06 ,  G06F9/50 ,  G06F12/0802 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0679 ,  G06F9/5083 ,  G06F12/0802 ,  G06F13/4221 ,  G06F2212/6042 ,  G06F2213/0026 ,  G06F2213/40

Abstract: Examples described herein include a system comprising: a processing unit package comprising: at least one core and at least one offload processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one offload processing device configurable to perform packet processing. In some examples, the at least one offload processing device is to allow mapping of packet processing pipeline stages of networking applications among software running on the at least one core and the at least one offload processing device to permit flexible entry, exit, and re-entry points among the at least one core and the at least one offload processing device.

公开(公告)号：US12026116B2

公开(公告)日：2024-07-02

申请号：US17134361

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Patrick G. Kutch ,  Andrey Chilikin ,  Niall D. McDonnell ,  Brian A. Keating ,  Naveen Lakkakula ,  Ilango S. Ganga ,  Venkidesh Krishna Iyer ,  Patrick Fleming ,  Lokpraveen Mosur

IPC: G06F13/40 ,  G06F3/06 ,  G06F9/50 ,  G06F12/0802 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0679 ,  G06F9/5083 ,  G06F12/0802 ,  G06F13/4221 ,  G06F2212/6042 ,  G06F2213/0026 ,  G06F2213/40

Abstract: Examples described herein include a system comprising: a processing unit package comprising: at least one core and at least one offload processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one offload processing device configurable to perform packet processing. In some examples, the at least one offload processing device is to allow mapping of packet processing pipeline stages of networking applications among software running on the at least one core and the at least one offload processing device to permit flexible entry, exit, and re-entry points among the at least one core and the at least one offload processing device.