公开(公告)号：US20240118826A1

公开(公告)日：2024-04-11

申请号：US17963313

申请日：2022-10-11

Applicant: Intel Corporation

Inventor： Amlan Ghosh ,  Feroze Merchant ,  Jaydeep Kulkarni ,  John R. Riley

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory device includes at least one bitcell coupled to a local bitline. The at least one bitcell includes multiple sets of a plurality of transistor devices. The first set of the plurality of transistor devices is configured to form a single write (1W) port for receiving digital data. The second set of the plurality of transistor devices is configured as an inverter pair. The inverter pair stores the digital data. The third set of the plurality of transistor devices is configured to form a single read (1R) port. The 1R port can be used to access the digital data stored at the inverter pair and output the digital data on the local bitline. The plurality of transistor devices includes an equal number of P-channel transistor devices and N-channel transistor devices.