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公开(公告)号：US11489526B2
公开(公告)日：2022-11-01
申请号：US16882407
申请日：2020-05-22
Applicant: Intel Corporation
Inventor： Andres Malavasi Mora , Jaydeep Kulkarni , Anupama Thaploo , Muhammad Khellah
IPC: H03K19/082 , H03K19/0175 , H03K19/0948
Abstract: Described is a level-shifter that can save area between voltage domains with limited voltage differential, and further save power by steering current between two power supply rails. The level-shifter comprises: an input to receive a first signal between a first reference rail and a second reference rail; an output to provide a second signal the first reference rail and a third reference rail, wherein in a voltage level of the third reference rail is higher than a voltage level of the second reference rail, and wherein a voltage level of the first reference is lower than the voltage level of the second reference rail and the third reference rail; and a circuitry coupled to the input and the output, wherein the circuitry is to steer current from the third reference rail to the second reference rail.
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公开(公告)号：US09905278B2
公开(公告)日：2018-02-27
申请号：US14859884
申请日：2015-09-21
Applicant: Intel Corporation
Inventor： Jaydeep Kulkarni
CPC classification number: G11C7/12 , G11C7/1048 , G11C8/08 , G11C8/10 , G11C17/12 , G11C2207/005
Abstract: Some embodiments include apparatuses and methods having non-volatile memory cells, a data line associated with a group of non-volatile memory cells of the non-volatile memory cells, a first transistor coupled to the data line and a node, a second transistor coupled to the node and an additional node, a pull-up component coupled to the node and a supply node, and an additional pull-up component coupled to the additional node and the supply node.
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公开(公告)号：US20170133061A1
公开(公告)日：2017-05-11
申请号：US15413171
申请日：2017-01-23
Applicant: Intel Corporation
Inventor： Hamid-Reza S. Bonakdar , Jaydeep Kulkarni
CPC classification number: G11C5/025 , G11C5/063 , G11C5/10 , G11C7/00 , G11C7/12 , G11C7/14 , G11C7/227 , G11C8/08 , G11C8/14 , G11C11/418
Abstract: Some embodiments include apparatuses having a first node to receive a supply voltage, a second node, a switching circuit to couple the first node to the second node and to decouple the first node from the second node, circuit blocks coupled to the second node and the switching circuit, and drivers coupled to the second node. Each of the circuit blocks includes a capacitor having a plate coupled to the second node. Each of the drivers is associated with a conductive line. The conductive line is associated with memory cells.
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公开(公告)号：US09552854B1
公开(公告)日：2017-01-24
申请号：US14937010
申请日：2015-11-10
Applicant: Intel Corporation
Inventor： Hamid-Reza S. Bonakdar , Jaydeep Kulkarni
CPC classification number: G11C5/025 , G11C5/063 , G11C5/10 , G11C7/00 , G11C7/12 , G11C7/14 , G11C7/227 , G11C8/08 , G11C8/14 , G11C11/418
Abstract: Some embodiments include apparatuses having a first node to receive a supply voltage, a second node, a switching circuit to couple the first node to the second node and to decouple the first node from the second node, circuit blocks coupled to the second node and the switching circuit, and drivers coupled to the second node. Each of the circuit blocks includes a capacitor having a plate coupled to the second node. Each of the drivers is associated with a conductive line. The conductive line is associated with memory cells.
Abstract translation: 一些实施例包括具有用于接收电源电压的第一节点的装置，第二节点，将第一节点耦合到第二节点的切换电路以及将第一节点与第二节点分离，耦合到第二节点的电路块和 开关电路和耦合到第二节点的驱动器。 每个电路块包括具有耦合到第二节点的板的电容器。 每个驱动器都与导线相关联。 导线与存储单元相关联。
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公开(公告)号：US10713333B2
公开(公告)日：2020-07-14
申请号：US15777249
申请日：2015-12-21
Applicant: Intel Corporation
Inventor： Farhana Sheikh , Ankit Sharma , Jaydeep Kulkarni
Abstract: A calculation circuit for calculating a transform of an input sequence may include a plurality of butterfly computation circuits configured to perform a plurality of butterfly computations and to produce a plurality of outputs during each of a plurality of computation stages, a wired routing network configured to route a first plurality of outputs of the plurality of butterfly computation circuits from a first computation stage of the plurality of computation stages as input to the plurality of butterfly computation circuits during a second computation stage of the plurality of computation stages according to a reconfigurable routing configuration, and routing control circuitry configured to modify the reconfigurable routing configuration for a third computation stage of the plurality of computation stages.
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Patent Agency Ranking
公开(公告)号：US10122347B2
公开(公告)日：2018-11-06
申请号：US15477913
申请日：2017-04-03
Applicant: Intel Corporation
Inventor： Minki Cho , Jaydeep Kulkarni , Carlos Tokunaga , Muhammad Khellah , James Tschanz
Abstract: An apparatus is provided which includes: a first power supply node; a second power supply node; a memory bit-cell coupled to the second power supply node; a circuitry coupled to the first and second power supply nodes, the circuitry to operate in a diode-connected mode; and a transistor coupled in parallel to the circuitry, wherein the transistor is controllable by a digital signal such that when the transistor is to turn on, it is to apply voltage and/or current stress to the memory bit-cell.
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公开(公告)号：US09767858B2
公开(公告)日：2017-09-19
申请号：US15413171
申请日：2017-01-23
Applicant: Intel Corporation
Inventor： Hamid-Reza S. Bonakdar , Jaydeep Kulkarni
CPC classification number: G11C5/025 , G11C5/063 , G11C5/10 , G11C7/00 , G11C7/12 , G11C7/14 , G11C7/227 , G11C8/08 , G11C8/14 , G11C11/418
Abstract: Some embodiments include apparatuses having a first node to receive a supply voltage, a second node, a switching circuit to couple the first node to the second node and to decouple the first node from the second node, circuit blocks coupled to the second node and the switching circuit, and drivers coupled to the second node. Each of the circuit blocks includes a capacitor having a plate coupled to the second node. Each of the drivers is associated with a conductive line. The conductive line is associated with memory cells.
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公开(公告)号：US10511224B2
公开(公告)日：2019-12-17
申请号：US15944214
申请日：2018-04-03
Applicant: Intel Corporation
Inventor： Jaydeep Kulkarni , Yong Shim , Pascal A. Meinerzhagen , Muhammad M. Khellah
Abstract: Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is arranged to transfer charge from the first supply power node to the second supply power node during a first time interval and to transfer charge from the second supply power node to the first supply power node during a second time interval.
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公开(公告)号：US10217495B2
公开(公告)日：2019-02-26
申请号：US15863382
申请日：2018-01-05
Applicant: Intel Corporation
Inventor： Jaydeep Kulkarni
Abstract: Some embodiments include apparatuses and methods having non-volatile memory cells, a data line associated with a group of non-volatile memory cells of the non-volatile memory cells, a first transistor coupled to the data line and a node, a second transistor coupled to the node and an additional node, a pull-up component coupled to the node and a supply node, and an additional pull-up component coupled to the additional node and the supply node.
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公开(公告)号：US20180287592A1
公开(公告)日：2018-10-04
申请号：US15477913
申请日：2017-04-03
Applicant: Intel Corporation
Inventor： Minki Cho , Jaydeep Kulkarni , Carlos Tokunaga , Muhammad Khellah , James Tschanz
IPC: H03K3/011 , H03K3/012 , G11C11/419 , G06F1/32
CPC classification number: H03K3/011 , G06F1/3275 , G11C11/413 , G11C11/419 , G11C29/04 , H03K3/012
Abstract: An apparatus is provided which includes: a first power supply node; a second power supply node; a memory bit-cell coupled to the second power supply node; a circuitry coupled to the first and second power supply nodes, the circuitry to operate in a diode-connected mode; and a transistor coupled in parallel to the circuitry, wherein the transistor is controllable by a digital signal such that when the transistor is to turn on, it is to apply voltage and/or current stress to the memory bit-cell.
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