公开(公告)号：US20200227525A1

公开(公告)日：2020-07-16

申请号：US16831558

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Dong JI ,  Guangyu HUANG ,  Deepak THIMMEGOWDA

IPC: H01L29/40 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L21/28 ,  H01L29/06

Abstract: A driver circuit for a three-dimensional (3D) memory device has a field management structure electrically coupled to a gate conductor. The field management structure causes an electric field peak in a vertical channel of the 3D memory device when a voltage differential exists between the source conductor and the drain conductor and the gate conductor is not biased. The electrical field peak can adjust the electrical response of the driver circuit, enabling the circuit to have a higher breakdown threshold voltage and improved drive current. Thus, the driver circuit can enable a scalable vertical string driver that is above the memory array instead of under the memory array circuitry.

公开(公告)号：US20230036595A1

公开(公告)日：2023-02-02

申请号：US17791176

申请日：2020-02-08

Applicant: Intel Corporation

Inventor： Deepak THIMMEGOWDA ,  Brian J. CLEEREMAN ,  Srivardhan GOWDA ,  Jui-Yen LIN ,  Liu LIU ,  Krishna PARAT ,  Jong Sun SEL ,  Baosuo ZHOU

IPC: H01L27/11582 ,  H01L27/11575 ,  G11C16/08

Abstract: An integrated circuit memory includes a first memory block and an adjacent second memory block. The first memory block comprises a first memory pillar around which a first memory cell is formed. The second memory block comprises a second memory pillar around which a second memory cell is formed. An isolation or slit area between the first and second memory blocks electrically isolates the first and second memory blocks. In an example, the slit area comprising a slit pillar around which no memory cells are formed. The slit pillar is a dummy pillar, and insulator material electrically isolates the slit pillar from a Word Line (WL) through which it passes. The isolation layer electrically can also isolate a (WL) of the first memory block from a corresponding WL of the second memory block. In an example, the slit pillar and the memory pillars have at least in part similar structures.

公开(公告)号：US20220102365A1

公开(公告)日：2022-03-31

申请号：US17032239

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Chang Wan HA ,  Chuan LIN ,  Deepak THIMMEGOWDA ,  Zengtao LIU ,  Binh N. NGO ,  Soo-yong PARK

IPC: H01L27/1158 ,  G11C16/04 ,  H01L29/10

Abstract: The total silicon area used by a plurality of high voltage transistors in an array of NAND cells is reduced by modifying the silicon area layout such that the size of the source and drain of each of the plurality of high voltage transistors is dependent on the maximum voltage to be applied to each of the source and drain for the respective one of the plurality of high voltage transistors.

公开(公告)号：US20200227429A1

公开(公告)日：2020-07-16

申请号：US16831623

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Dong JI ,  Guangyu HUANG ,  Deepak THIMMEGOWDA

IPC: H01L27/11573 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/06 ,  H01L29/04 ,  H01L29/16 ,  H01L29/22 ,  H01L29/49 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

Abstract: A driver circuit for a three-dimensional (3D) memory device has a super junction structure as a field management structure. The super junction structure could be referred to as an extended junction structure, which distributes the electrical field of the junction between the vertical channel and the gate conductor for a string driver. The vertical channel includes a channel conductor to connect vertically between a source conductor and a drain conductor. The extended junction structure extends in parallel with the vertical channel conductor, extending vertically toward the drain conductor, having a height greater than a height of the gate conductor.

公开(公告)号：US20180331034A1

公开(公告)日：2018-11-15

申请号：US16045369

申请日：2018-07-25

Applicant: Intel Corporation

Inventor： Deepak THIMMEGOWDA ,  Aaron YIP ,  Mark HELM ,  Yongna LI

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11524 ,  H01L27/11578

Abstract: An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.

公开(公告)号：US20170287833A1

公开(公告)日：2017-10-05

申请号：US15085151

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Deepak THIMMEGOWDA ,  Aaron YIP ,  Mark HELM ,  Yongna LI

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/5226 ,  H01L27/11524 ,  H01L27/11578 ,  H01L28/00

Abstract: An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.