公开(公告)号：US20170271501A1

公开(公告)日：2017-09-21

申请号：US15505558

申请日：2014-09-24

Applicant: Intel Corporation

Inventor： Uygar E. AVCI ,  Rafael RIOS ,  Kelin J. KUHN ,  Ian A. YOUNG ,  Justin R. WEBER

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/16 ,  H01L29/24 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/66795 ,  H01L29/7391

Abstract: Described is a TFET comprising: a nanowire having doped regions for forming source and drain regions, and an un-doped region for coupling to a gate region; and a first termination material formed over the nanowire; and a second termination material formed over a section of the nanowire overlapping the gate and source regions. Described is another TFET comprising: a first section of a nanowire having doped regions for forming source and drain regions, and an undoped region for coupling to a gate region; a second section of the nanowire extending orthogonal to the first section, the second section formed next to the gate and source regions; and a termination material formed over the first and second sections of the nanowire.