公开(公告)号：US20220310901A1

公开(公告)日：2022-09-29

申请号：US17211736

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Kaan OGUZ ,  Tanay GOSAVI ,  Emily WALKER ,  Chia-Ching LIN ,  Ian A. YOUNG

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/06 ,  H01L43/10

Abstract: Spin orbit torque (SOT) devices with topological insulator (TI) and heavy metal insert are described. In an example, an integrated circuit structure includes a spin orbit coupling (SOC) interconnect including a TI material. A magnetic layer is above the SOC interconnect. An insert layer includes a heavy metal between and in contact with the TI material and the magnetic layer.

公开(公告)号：US20190065151A1

公开(公告)日：2019-02-28

申请号：US16145569

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Gregory K. CHEN ,  Raghavan KUMAR ,  Huseyin Ekin SUMBUL ,  Phil KNAG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Ian A. YOUNG

IPC: G06F7/544 ,  G06F9/30 ,  G06F7/501 ,  G06F17/16

Abstract: A memory device that includes a plurality subarrays of memory cells to store static weights and a plurality of digital full-adder circuits between subarrays of memory cells is provided. The digital full-adder circuit in the memory device eliminates the need to move data from a memory device to a processor to perform machine learning calculations. Rows of full-adder circuits are distributed between sub-arrays of memory cells to increase the effective memory bandwidth and reduce the time to perform matrix-vector multiplications in the memory device by performing bit-serial dot-product primitives in the form of accumulating m 1-bit x n-bit multiplications.

公开(公告)号：US20190042949A1

公开(公告)日：2019-02-07

申请号：US16147143

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Ian A. YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Gregory K. CHEN ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin Ekin SUMBUL

IPC: G06N3/10 ,  G06F17/50 ,  G06N3/063

Abstract: A semiconductor chip is described. The semiconductor chip includes a compute-in-memory (CIM) circuit to implement a neural network in hardware. The semiconductor chip also includes at least one output that presents samples of voltages generated at a node of the CIM circuit in response to a range of neural network input values applied to the CIM circuit to optimize the CIM circuit for the neural network.

公开(公告)号：US20190034360A1

公开(公告)日：2019-01-31

申请号：US15660819

申请日：2017-07-26

Applicant: Intel Corporation

Inventor： Kaushik VAIDYANATHAN ,  Daniel H. MORRIS ,  Uygar E. AVCI ,  Ian A. YOUNG ,  Tanay KARNIK ,  Huichu LIU

IPC: G06F13/10 ,  G06F9/445 ,  G06F1/26

Abstract: Described is an apparatus which comprises: a first electrical path comprising at least one driver and receiver; and a second electrical path comprising at least one driver and receiver, wherein the first and second electrical paths are to receive a same input signal, wherein the first electrical path and the second electrical path are parallel to one another and have substantially the same propagation delays, and wherein the second electrical path is enabled during a first operation mode and disabled during a second operation mode.

公开(公告)号：US20180158588A1

公开(公告)日：2018-06-07

申请号：US15569978

申请日：2015-06-24

Applicant: Intel Corporation

Inventor： Sasikanth MANIPATRUNI ,  Anurag CHAUDHRY ,  Dmitri E. NIKONOV ,  Ian A. YOUNG

IPC: H01F10/32 ,  H01L43/10 ,  G11C11/16 ,  G11C11/155 ,  H03K19/16 ,  H01L43/08

CPC classification number: H01F10/3268 ,  G11C11/155 ,  G11C11/1675 ,  H01F10/265 ,  H01L43/08 ,  H01L43/10 ,  H03K19/16 ,  H03K19/18

Abstract: Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a corresponding spin current; and a stack of metal layers configured to convert the corresponding spin current to a second charge current, wherein the stack of metal layers is coupled to the input magnet.

公开(公告)号：US20170054006A1

公开(公告)日：2017-02-23

申请号：US15118843

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： Uygar E. AVCI ,  Roza KOTLYAR ,  Ian A. YOUNG

IPC: H01L29/66 ,  H01L23/66 ,  G06F3/041 ,  H01L29/786

CPC classification number: H01L29/66977 ,  G06F3/041 ,  H01L21/18 ,  H01L23/66 ,  H01L29/165 ,  H01L29/205 ,  H01L29/42312 ,  H01L29/66356 ,  H01L29/66742 ,  H01L29/7391 ,  H01L29/78 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78696 ,  H01L29/88 ,  H01L2223/6677

Abstract: Described is a tunneling field effect transistor (TFET), comprising: a drain region having a first conductivity type; a source region having a second conductivity type opposite of the first conductivity type; a gate region to cause formation of a channel region between the source and drain regions; and a pocket disposed near a junction of the source region, wherein the pocket region formed from a material having lower percentage of one type of atom than percentage of the one type of atom in the source, channel, and drain regions.

Abstract translation: 描述了隧道场效应晶体管（TFET），其包括：具有第一导电类型的漏极区; 源区域，具有与第一导电类型相反的第二导电类型; 栅极区域，用于在源区和漏区之间形成沟道区; 以及设置在所述源极区域的接合点附近的口袋，其中所述口袋区域由具有比所述源极，沟道和漏极区域中的一种类型的原子的百分比低的一种类型的原子的比例低的材料形成。

公开(公告)号：US20160373108A1

公开(公告)日：2016-12-22

申请号：US15122150

申请日：2014-03-27

Applicant: INTEL CORPORATION

Inventor： Daniel H. MORRIS ,  Uygar E. AVCI ,  Rafael RIOS ,  Ian A. YOUNG

IPC: H03K17/693 ,  H01L29/775 ,  G11C5/06 ,  H01L27/092

CPC classification number: H03K17/693 ,  G11C5/066 ,  H01L27/092 ,  H01L29/7391 ,  H01L29/775 ,  H03K19/094 ,  H03K19/0948

Abstract: Multiplexor circuits with Tunneling field effect transistors (TFET) devices are described. For example, a multiplexor circuit includes a first set of tunneling field effect transistor (TFET) devices that are coupled to each other. The first set of TFET devices receive a first data input signal, a first select signal, and a second select signal. A second set of TFET devices are coupled to each other and receive a second data input signal, the first select signal, and the second select signal. An output terminal is coupled to the first and second set of TFETs. The output terminal generates an output signal of the multiplexor circuit.

Abstract translation: 描述了具有隧道场效应晶体管（TFET）器件的多路复用器电路。 例如，多路复用器电路包括彼此耦合的第一组隧道场效应晶体管（TFET）器件。 第一组TFET器件接收第一数据输入信号，第一选择信号和第二选择信号。 第二组TFET器件彼此耦合并且接收第二数据输入信号，第一选择信号和第二选择信号。 输出端子耦合到第一和第二组TFET。 输出端产生多路复用器电路的输出信号。

公开(公告)号：US20160300612A1

公开(公告)日：2016-10-13

申请号：US15036761

申请日：2013-12-24

Applicant: Sasikanth MANIPATRUNI ,  Ian A. YOUNG ,  INTEL CORPORATION

Inventor： Sasikanth MANIPATRUNI ,  Ian A. YOUNG

IPC: G11C14/00 ,  G11C11/16 ,  H01L27/108 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  G11C13/00 ,  H01L27/22

CPC classification number: G11C14/0036 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0069 ,  G11C14/0018 ,  G11C14/0045 ,  H01L27/10832 ,  H01L27/1087 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H04L9/0897

Abstract: Described is an apparatus for a hybrid eDRAM and MRAM memory cell comprising: a capacitor having a first terminal and a second terminal; a first transistor having a gate terminal coupled to a first word line (WL), a source/drain terminal coupled to bit line (BL), and drain/source terminal coupled to the first terminal of the capacitor; a resistive memory element having a first terminal and a second terminal, the first terminal of the resistive memory element device coupled to the first terminal of the capacitor; and a second transistor having a gate terminal coupled to a second WL, a source/drain terminal coupled to source line (SL), and drain/source terminal coupled to the second terminal of the resistive memory element device.

Abstract translation: 描述了一种用于混合eDRAM和MRAM存储单元的装置，包括：具有第一端子和第二端子的电容器; 第一晶体管，其具有耦合到第一字线（WL）的栅极端子，耦合到位线（BL）的源极/漏极端子以及耦合到所述电容器的所述第一端子的漏极/源极端子; 具有第一端子和第二端子的电阻性存储元件，所述电阻式存储元件器件的所述第一端子耦合到所述电容器的第一端子; 以及第二晶体管，其具有耦合到第二WL的栅极端子，耦合到源极线（SL）的源极/漏极端子以及耦合到所述电阻性存储器件器件的所述第二端子的漏极/源极端子。

公开(公告)号：US20210167182A1

公开(公告)日：2021-06-03

申请号：US16700757

申请日：2019-12-02

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Ashish Verma PENUMATCHA ,  Sou-Chi CHANG ,  Devin MERRILL ,  I-Cheng TUNG ,  Nazila HARATIPOUR ,  Jack T. KAVALIEROS ,  Ian A. YOUNG ,  Matthew V. METZ ,  Uygar E. AVCI ,  Chia-Ching LIN ,  Owen LOH ,  Shriram SHIVARAMAN ,  Eric Charles MATTSON

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234

Abstract: A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack. A selector element is above the metal layer.

公开(公告)号：US20200312950A1

公开(公告)日：2020-10-01

申请号：US16369737

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Nazila HARATIPOUR ,  Chia-Ching LIN ,  Sou-Chi CHANG ,  Ashish Verma PENUMATCHA ,  Owen LOH ,  Mengcheng LU ,  Seung Hoon SUNG ,  Ian A. YOUNG ,  Uygar AVCI ,  Jack T. KAVALIEROS

IPC: H01L49/02 ,  H01L27/11585 ,  H01L23/522 ,  H01G4/30 ,  H01G4/012

Abstract: A capacitor is disclosed that includes a first metal layer and a seed layer on the first metal layer. The seed layer includes a polar phase crystalline structure. The capacitor also includes a ferroelectric layer on the seed layer and a second metal layer on the ferroelectric layer.