公开(公告)号：US20240004810A1

公开(公告)日：2024-01-04

申请号：US17856632

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Gary Brian Wallichs ,  Andrew Martyn Draper ,  Kye Howe Wong ,  Kalen Brunham ,  Jeffrey Edward Erickson

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/28 ,  G06F15/167

CPC classification number: G06F13/1673 ,  G06F13/4072 ,  G06F13/28 ,  G06F15/167

Abstract: A system including a host device and an integrated circuit. The host device includes a host memory, the host memory storing configuration data. The integrated circuit device includes an integrated circuit and a direct memory access circuitry. The direct memory access circuitry pulls the configuration data from the host memory. The direct memory access circuitry also programs the integrated circuit based on the configuration data.

公开(公告)号：US20240037305A1

公开(公告)日：2024-02-01

申请号：US18481935

申请日：2023-10-05

Applicant: Intel Corporation

Inventor： Kalen Brunham ,  Jakob Engblom

IPC: G06F30/3308 ,  G06F30/327

CPC classification number: G06F30/3308 ,  G06F30/327 ,  G06F2111/20

Abstract: Systems or methods of the present disclosure may provide receiving configuration data corresponding to a circuit design for programmable logic circuitry. A first intellectual property (IP) block is configured using parameterization data of the configuration data. A stub model is generated for a second IP block using interconnect and register data of the configuration data. A chip-level model is generated that represents the circuit design based on the first IP block, the stub model, and memory map data of the configuration data. The chip-level model is consumable by a virtual platform simulator.