公开(公告)号：US20240312942A1

公开(公告)日：2024-09-19

申请号：US18120904

申请日：2023-03-13

Applicant: Intel Corporation

Inventor： Vidya JAYARAM ,  Karan BHANGAONKAR ,  Chandrasekharan NAIR

IPC: H01L23/00 ,  H01L21/311 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L24/19 ,  H01L21/31116 ,  H01L23/49816 ,  H01L23/5226 ,  H01L24/16 ,  H01L2224/16012 ,  H01L2224/19

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a layer with a film over the layer. In an embodiment, the film is an inorganic material. In an embodiment, the package substrate may further comprise a plurality of electrically conductive traces over the film, and a seed layer between the plurality of electrically conductive traces and the film. In an embodiment, edges of the seed layer are substantially aligned with edges of the plurality of electrically conductive traces.