公开(公告)号：US10348634B2

公开(公告)日：2019-07-09

申请号：US14979131

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Keith D. Underwood ,  Charles A Giefer ,  Bruce M. Pirie ,  Karl P. Brummel

IPC: H04L12/801 ,  H04L12/807 ,  H04L29/12

Abstract: Technologies for tracking out-of-order network packets include a target computing node coupled to a source computing node via a communication channel. The target computing node is configured to allocate a small window in memory in which to store a bit mask corresponding to a number of out-of-order network packets received from the source computing node via the communication channel. The target computing node is further configured to update the bit mask in the small window upon receiving an out-of-order network packet from the source computing node. The target computing node is additionally configured to allocate a large window in memory in response to a determination the size of the bit mask is larger than the size of the small window, store the bit mask in the large window, and store a pointer to the large window in the small window. Other embodiments are described and claimed.

公开(公告)号：US20170180265A1

公开(公告)日：2017-06-22

申请号：US14979131

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Keith D. Underwood ,  Charles A. Giefer ,  Bruce M. Pirie ,  Karl P. Brummel

IPC: H04L12/801 ,  H04L12/807 ,  H04L29/12

CPC classification number: H04L47/34 ,  H04L47/27 ,  H04L61/6095

Abstract: Technologies for tracking out-of-order network packets include a target computing node coupled to a source computing node via a communication channel. The target computing node is configured to allocate a small window in memory in which to store a bit mask corresponding to a number of out-of-order network packets received from the source computing node via the communication channel. The target computing node is further configured to update the bit mask in the small window upon receiving an out-of-order network packet from the source computing node. The target computing node is additionally configured to allocate a large window in memory in response to a determination the size of the bit mask is larger than the size of the small window, store the bit mask in the large window, and store a pointer to the large window in the small window. Other embodiments are described and claimed.

公开(公告)号：US11172016B2

公开(公告)日：2021-11-09

申请号：US15474833

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Karl P. Brummel ,  Charles A. Giefer ,  Nathan S. Miller ,  Keith D. Underwood

IPC: H04L29/08 ,  H04L12/801 ,  H04L12/823 ,  H04L12/851 ,  H04L12/807 ,  H04L12/835

Abstract: A computing device, a method, and a system to enforce concurrency limits within a network fabric. The computing device includes a memory device; and a network interface controller coupled to the memory device. The network interface controller includes circuitry to communicate with a plurality of target computing devices in a network fabric. The circuitry is configured to generate packets for transmission to respective ones of a plurality of target nodes. For each packet addressed to its corresponding target node, the circuitry is to determine whether transmitting the packet would violate the target node's concurrency limit. If transmitting the packet would not violate the target node's concurrency limit, the circuitry is to transmit the packet to the target node. However, if transmitting the packet would violate the target node's concurrency limit, the circuitry would store the packet in a retransmit buffer of the computing device, where the retransmit buffer is to further store already transmitted packets flagged for retransmission. The circuitry would then transmit the packet from the retransmit buffer when transmitting the packet from the retransmit buffer would not violate the target node's concurrency limit.

公开(公告)号：US20180287904A1

公开(公告)日：2018-10-04

申请号：US15474833

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Karl P. Brummel ,  Charles A. Giefer ,  Nathan S. Miller ,  Keith D. Underwood

IPC: H04L12/26 ,  H04L29/08

Abstract: A computing device, a method, and a system to enforce concurrency limits within a network fabric. The computing device includes a memory device; and a network interface controller coupled to the memory device. The network interface controller includes circuitry to communicate with a plurality of target computing devices in a network fabric. The circuitry is configured to generate packets for transmission to respective ones of a plurality of target nodes. For each packet addressed to its corresponding target node, the circuitry is to determine whether transmitting the packet would violate the target node's concurrency limit. If transmitting the packet would not violate the target node's concurrency limit, the circuitry is to transmit the packet to the target node. However, if transmitting the packet would violate the target node's concurrency limit, the circuitry would store the packet in a retransmit buffer of the computing device, where the retransmit buffer is to further store already transmitted packets flagged for retransmission. The circuitry would then transmit the packet from the retransmit buffer when transmitting the packet from the retransmit buffer would not violate the target node's concurrency limit.

公开(公告)号：US10044626B2

公开(公告)日：2018-08-07

申请号：US14757993

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Keith Underwood ,  Charles Giefer ,  Mark Debbage ,  Karl P. Brummel ,  Nathan Miller ,  Bruce Pirie

IPC: H04L12/801 ,  H04L12/807 ,  H04L12/869 ,  H04L1/16 ,  H04L1/18 ,  H04L29/06

Abstract: In an embodiment, an out-of-order, reliable, end-to-end protocol is provided that can enable direct user-level data placement and atomic operations between nodes of a multi-node network. The protocol may be optimized for low-loss environments such as High Performance Computing (HPC) applications, and may enable loss detection and de-duplication of packets through the use of a robust window state manager at a target node. A multi-node network implementing the protocol may have increased system reliability, packet throughput, and increased tolerance for adaptively routed traffic, while still allowing atomic operations to be idempotently applied directly to a user memory location.