公开(公告)号：US10963183B2

公开(公告)日：2021-03-30

申请号：US15463005

申请日：2017-03-20

Applicant: Intel Corporation

Inventor： James Dinan ,  Keith D. Underwood ,  Sayantan Sur ,  Charles A. Giefer ,  Mario Flajslik

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/28

Abstract: Technologies for fine-grained completion tracking of memory buffer accesses include a compute device. The compute device is to establish multiple counter pairs for a memory buffer. Each counter pair includes a locally managed offset and a completion counter. The compute device is also to receive a request from a remote compute device to access the memory buffer, assign one of the counter pairs to the request, advance the locally managed offset of the assigned counter pair by the amount of data to be read or written, and advance the completion counter of the assigned counter pair as the data is read from or written to the memory buffer. Other embodiments are also described and claimed.

公开(公告)号：US10693818B2

公开(公告)日：2020-06-23

申请号：US16189323

申请日：2018-11-13

Applicant: Intel Corporation

Inventor： Keith D. Underwood ,  Charles A. Giefer

IPC: H04L12/861

Abstract: Packet tracking techniques for communication networks are described. In an example embodiment, an apparatus may comprise circuitry, a tracking component for execution by the circuitry to, in response to a request of an initiator device to establish a packet transfer session, determine whether tracking information for the packet transfer session can be locally maintained and in response to a determination that the tracking information for the packet transfer session cannot be locally maintained, identify one or more tracking parameters for retention at the initiator device, and a communication component for execution by the circuitry to send an acceptance message to grant the request of the initiator device to establish the packet transfer session, the acceptance message to indicate a request for retention of the one or more tracking parameters. Other embodiments are described and claimed.

公开(公告)号：US20190044875A1

公开(公告)日：2019-02-07

申请号：US15865743

申请日：2018-01-09

Applicant: Intel Corporation

Inventor： Ravi Murty ,  Keith D. Underwood ,  Ravindra Babu Ganapathi ,  Andrew Friedley ,  Vignesh Trichy Ravi

IPC: H04L12/805 ,  H04L12/707

Abstract: Particular embodiments described herein provide for a system for enabling the communication of a large message using multiple network interface controllers (NICs). The system can be configured to determine that a message to communicate to a receiver over a network is above a threshold, determine a plurality of NICs to be used to communicate the message, create a manifest that includes an identifier of each of the plurality of NICs, and communicate the manifest to the receiver using a multi-unit message. In an example, the multi-unit message is communicated using a PUT command and the receiver can analyze the manifest and use a GET command to pull the message from the plurality of NICs.

公开(公告)号：US20180267742A1

公开(公告)日：2018-09-20

申请号：US15463005

申请日：2017-03-20

Applicant: Intel Corporation

Inventor： James Dinan ,  Keith D. Underwood ,  Sayantan Sur ,  Charles A. Giefer ,  Mario Flajslik

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0616 ,  G06F3/0656 ,  G06F3/0673 ,  G06F13/1673 ,  G06F13/28

Abstract: Technologies for fine-grained completion tracking of memory buffer accesses include a compute device. The compute device is to establish multiple counter pairs for a memory buffer. Each counter pair includes a locally managed offset and a completion counter. The compute device is also to receive a request from a remote compute device to access the memory buffer, assign one of the counter pairs to the request, advance the locally managed offset of the assigned counter pair by the amount of data to be read or written, and advance the completion counter of the assigned counter pair as the data is read from or written to the memory buffer. Other embodiments are also described and claimed.

公开(公告)号：US09973417B2

公开(公告)日：2018-05-15

申请号：US15256390

申请日：2016-09-02

Applicant: Intel Corporation

Inventor： Keith D. Underwood ,  Steffen Kosinski ,  Jaroslaw Topp ,  Jan Norden ,  Michael Redeker

IPC: H04L29/04 ,  H04L12/721 ,  G06F15/167 ,  G06F13/38 ,  H04L12/773 ,  H04L1/12 ,  H04L12/26 ,  H04L12/801 ,  H04L29/08 ,  H04L1/18

CPC classification number: H04L45/38 ,  G06F13/385 ,  G06F15/167 ,  H04L1/12 ,  H04L1/1835 ,  H04L43/103 ,  H04L45/60 ,  H04L47/34 ,  H04L67/10 ,  Y02D10/14 ,  Y02D10/151

Abstract: Methods related to communication between and within nodes in a high performance computing system are presented. Processing time for message exchange between a processing unit and a network controller interface in a node is reduced. Resources required to manage application state in the network interface controller are minimized. In the network interface controller, multiple contexts are multiplexed into one physical Direct Memory Access engine. Virtual to physical address translation in the network interface controller is accelerated by using a plurality of independent caches, with each level of the page table hierarchy cached in an independent cache. A memory management scheme for data structures distributed between the processing unit and the network controller interface is provided. The state required to implement end-to-end reliability is reduced by limiting the transmit sequence number space to the currently in-flight messages.

公开(公告)号：US11277350B2

公开(公告)日：2022-03-15

申请号：US15865743

申请日：2018-01-09

Applicant: Intel Corporation

Inventor： Ravi Murty ,  Keith D. Underwood ,  Ravindra Babu Ganapathi ,  Andrew Friedley ,  Vignesh Trichy Ravi

IPC: H04L1/00 ,  H04L47/36 ,  H04L45/24

Abstract: Particular embodiments described herein provide for a system for enabling the communication of a large message using multiple network interface controllers (NICs). The system can be configured to determine that a message to communicate to a receiver over a network is above a threshold, determine a plurality of NICs to be used to communicate the message, create a manifest that includes an identifier of each of the plurality of NICs, and communicate the manifest to the receiver using a multi-unit message. In an example, the multi-unit message is communicated using a PUT command and the receiver can analyze the manifest and use a GET command to pull the message from the plurality of NICs.

公开(公告)号：US20190044872A1

公开(公告)日：2019-02-07

申请号：US15941490

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Ravindra Babu Ganapathi ,  Andrew Friedley ,  Jim M. Snow ,  Keith D. Underwood

IPC: H04L12/823 ,  H04L12/801 ,  H04L12/835

Abstract: Technologies for targeted flow control recovery include a target computing device which detects whether resources of the target computing device are sufficient to process received messages from at least one source computing device and, in response to a determination that the resources are insufficient, (i) drops received message(s) from the affected source computing device(s) and (ii) determines whether to issue a targeted flow control recovery (i.e., at one of the source computing devices) or a global targeted flow control recovery (i.e., at all of the source computing devices) to instruct the source computing device(s) to stop transmitting messages to the target computing device. The target computing device, upon completion of the flow control recovery, atomically enables a table entry for which resources to process the received message(s) have been allocated and transmits a targeted or global resume transmission message to the source computing device(s) to instruct the source computing device to resume transmitting messages to the target computing device.

公开(公告)号：US20170085625A1

公开(公告)日：2017-03-23

申请号：US14858051

申请日：2015-09-18

Applicant: Intel Corporation

Inventor： James Dinan ,  Mario Flajslik ,  Keith D. Underwood

IPC: H04L29/08 ,  H04L12/743 ,  H04L12/863

Abstract: Technologies for handling message passing interface receive operations include a compute node to determine a plurality of parameters of a receive entry to be posted and determine whether the plurality of parameters includes a wildcard entry. The compute node generates a hash based on at least one parameter of the plurality of parameters in response to determining that the plurality of parameters does not include the wildcard entry and appends the receive entry to a list in a bin of a posted receive data structure, wherein the bin is determined based on the generated hash. The compute node further tracks the wildcard entry in the posted receive data structure in response to determining the plurality of parameters includes the wildcard entry and appends the receive entry to a wildcard list of the posted receive data structure in response to tracking the wildcard entry.

公开(公告)号：US11190973B2

公开(公告)日：2021-11-30

申请号：US15450651

申请日：2017-03-06

Applicant: Intel Corporation

Inventor： Eric R. Borch ,  Keith D. Underwood

IPC: H04W28/02 ,  H04W72/04 ,  H04L12/931

Abstract: Technologies for link-bandwidth-aware routing are disclosed. In order to avoid congestion while still allowing link bandwidth to be decreased in order to save power, a network switch may select a port to send a packet over based on the present link bandwidth of the data links connected to the various output ports of the network switch. The network switch preferentially sends the packet over the minimal output port, or, if the minimal output port is congested, over one of the ports with the highest available link bandwidth. If the link bandwidth of the data link connected to the selected output port is not high enough, the network switch will automatically dynamically increase the link bandwidth of the data link as necessary.

公开(公告)号：US11188394B2

公开(公告)日：2021-11-30

申请号：US15941984

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： James Dinan ,  Mario Flajslik ,  Timo Schneider ,  Keith D. Underwood

IPC: G06F9/46 ,  G06F9/52

Abstract: Technologies for synchronizing triggered operations include a host fabric interface (HFI) of a compute device configured to receive an operation execution command associated with a triggered operation that has been fired and determine whether the operation execution command includes an instruction to update a table entry of a table managed by the HFI. Additionally, the HFI is configured to issue, in response to a determination that the operation execution command includes the instruction to update the table entry, a triggered list enable (TLE) operation and a triggered list disable (TLD) operation to a table manager of the HFI and disable a corresponding table entry in response to the TLD operation having been triggered, the identified table entry. The HFI is further configured to execute one or more command operations associated with the received operation execution command and re-enable, in response to the TLE operation having been triggered, the table entry. Other embodiments are described herein.