公开(公告)号：US20240281150A1

公开(公告)日：2024-08-22

申请号：US18650966

申请日：2024-04-30

Applicant: Intel Corporation

Inventor： Yi ZENG ,  Kaushik BALASUBRAMANIAN ,  Eti BAYEVSKY ,  Yuli BARCOHEN ,  Lukasz GOLAWSKI ,  Yaniv NISSIM

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: Examples described herein relate to an interface to a serial connection and circuitry to: prior to issuance of a read request to a device, issue a command to the device to identify data to be requested to be read and based on an indicator that the identified data is available to be read, send the read request for the identified data via the interface to the device. The command can include an operational code, a starting address, and length.

公开(公告)号：US20250004896A1

公开(公告)日：2025-01-02

申请号：US18217245

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Sridharan SAKTHIVELU ,  Kaushik BALASUBRAMANIAN ,  Krishna SURYA

IPC: G06F11/27

Abstract: Methods and apparatus to implement proactive hardware error screening are disclosed. In one embodiment, a computer processing system includes a plurality of computational units to execute tasks for one or more applications; a plurality of sensors collects measurement data of the plurality of computational units, to collect measurement data of the plurality of computational units; a data structure indicating hardware health statuses of the plurality of computational units determined based on the measurement data is stored in a storage; and the plurality of computational units is scheduled to perform task execution on the computer processing system for the one or more applications based on the hardware health statuses of the plurality of computational units indicated in the data structure, wherein a first computational unit is excluded from the task execution when a corresponding first hardware health status of the first computational unit indicates an impending hardware failure.

公开(公告)号：US20240152421A1

公开(公告)日：2024-05-09

申请号：US18477611

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Rajesh POORNACHANDRAN ,  Kaushik BALASUBRAMANIAN ,  Karan PUTTANNAIAH

IPC: G06F11/07 ,  G06F9/455

CPC classification number: G06F11/0793 ,  G06F9/45558 ,  G06F11/0712 ,  G06F2009/45591

Abstract: An apparatus is provided. The apparatus comprises interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to receive a request from a virtual machine to execute a task, receive a service-level agreement, SLA, from the virtual machine indicating a desired feature of scanning a computing resource to execute the task for errors, and scan the computing resource for errors based on the SLA.