公开(公告)号：US20240159829A1

公开(公告)日：2024-05-16

申请号：US18551879

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Min LIU ,  Jaemon FRANKO ,  Xia JIN ,  Xiang LI ,  Jiaqi LIU ,  Krishna SURYA

IPC: G01R31/3185

CPC classification number: G01R31/318591 ,  G01R31/31853 ,  G01R31/318547

Abstract: A processing device (30, 710) for reducing scan traffic is provided. The processing device (30, 710) comprises one or more interfaces (32, 718) configured to transmit information to at least one register access interface (759, 761) and processing circuitry (34) configured to control the one or more interfaces. Further, the processing circuitry (34) is configured to obtain register parameters of at least one functional unit (760, 762) of a processing unit (750) and to generate an improved bulk register comprising the register parameters of the at least one functional unit.

公开(公告)号：US20210165730A1

公开(公告)日：2021-06-03

申请号：US17175488

申请日：2021-02-12

Applicant: Intel Corporation

Inventor： Krishna SURYA ,  William L. HINES

IPC: G06F11/36 ,  G06F11/34 ,  G06F11/32 ,  G06F11/07

Abstract: Methods, apparatus, and software for hardware reliability diagnostics and failure detection via parallel software computation and compare. Parallel testing is performed on hardware resources such as processor cores, accelerators, and Other Processing Units (XPUs) using test algorithms such as encryption/decryption. The results of the testing (the algorithm outputs) are compared to detect errant hardware. Comparison may be across cores (via execution of software-based algorithms), across accelerators/XPUs (via algorithms implement in hardware) or between cores and accelerators/XPUs. Techniques are disclosed to enable all cores to be tested while a platform is performing a workload, such as in a data center environment, wherein unused cores are used for testing, with workloads being migrated between cores between tests.

公开(公告)号：US20250004896A1

公开(公告)日：2025-01-02

申请号：US18217245

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Sridharan SAKTHIVELU ,  Kaushik BALASUBRAMANIAN ,  Krishna SURYA

IPC: G06F11/27

Abstract: Methods and apparatus to implement proactive hardware error screening are disclosed. In one embodiment, a computer processing system includes a plurality of computational units to execute tasks for one or more applications; a plurality of sensors collects measurement data of the plurality of computational units, to collect measurement data of the plurality of computational units; a data structure indicating hardware health statuses of the plurality of computational units determined based on the measurement data is stored in a storage; and the plurality of computational units is scheduled to perform task execution on the computer processing system for the one or more applications based on the hardware health statuses of the plurality of computational units indicated in the data structure, wherein a first computational unit is excluded from the task execution when a corresponding first hardware health status of the first computational unit indicates an impending hardware failure.