公开(公告)号：US11188255B2

公开(公告)日：2021-11-30

申请号：US15938740

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Yu Ying Ong ,  Kevin Chao Ing Teoh

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16 ,  G06F13/00 ,  G06F13/28

Abstract: An integrated circuit may include a memory controller circuit for communicating with an off-chip memory device. The memory controller is operable in a read-write major mode that is capable of dynamically adapting to any memory traffic pattern, which results in improved memory scheduling efficiency across different user applications. The memory controller may include at least a write command queue, a read command queue, an arbiter, and a command scheduler. The command scheduler may monitor a write command count, a read command count, a write stall count, and a read stall count to determine whether to dynamically adjust a read burst threshold setting and a write burst threshold setting.

公开(公告)号：US20190303039A1

公开(公告)日：2019-10-03

申请号：US15938740

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Yu Ying Ong ,  Kevin Chao Ing Teoh

IPC: G06F3/06 ,  G06F13/16

Abstract: An integrated circuit may include a memory controller circuit for communicating with an off-chip memory device. The memory controller is operable in a read-write major mode that is capable of dynamically adapting to any memory traffic pattern, which results in improved memory scheduling efficiency across different user applications. The memory controller may include at least a write command queue, a read command queue, an arbiter, and a command scheduler. The command scheduler may monitor a write command count, a read command count, a write stall count, and a read stall count to determine whether to dynamically adjust a read burst threshold setting and a write burst threshold setting.