公开(公告)号：US20240220445A1

公开(公告)日：2024-07-04

申请号：US18147829

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Kannan Rajamani ,  Kameran Azadet ,  Kevin Kinney ,  Thomas Smith ,  Zoran Zivkovic

IPC: G06F15/80 ,  G06F9/50 ,  G06F9/54

CPC classification number: G06F15/80 ,  G06F9/5027 ,  G06F9/54

Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture functions to maintain synchronization between data samples to be transmitted, feedback data samples measured from an observed previous transmission of data samples, and output data samples that comprise the data samples from previous data transmissions, which may include data samples prior to or after the application of DPD terms. The architecture enables synchronization amongst several transmission channels, and provides for high flexibility with respect to timing flows and the movement and processing of data blocks.

公开(公告)号：US12072835B2

公开(公告)日：2024-08-27

申请号：US17851739

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Kevin Kinney ,  Zoran Zivkovic

IPC: G06F15/80 ,  G06F1/12

CPC classification number: G06F15/80 ,  G06F1/12

Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture implements a data driven synchronization process to maintain synchronization between the programmable elements (PEs) of the programmable processing array. The hybrid architecture implements a timer-based solution to ensure data-driven synchronization between the PEs of the programmable processing array meets the time-based synchronization requirements of the overall system. The timers function to introduce a delay or latency to the time required by each of the PEs of the programmable processing array to perform their respective tasks, thereby forcing the hardware blocks to wait to receive the processed data samples output via the PEs and perform their hardware-based computations.

公开(公告)号：US20240008045A1

公开(公告)日：2024-01-04

申请号：US17853194

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Kannan Rajamani ,  Kameran Azadet ,  Kevin Kinney ,  Thomas Smith ,  Zoran Zivkovic

IPC: H04W72/04 ,  H04J3/06

CPC classification number: H04W72/042 ,  H04J3/0661

Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture functions to maintain synchronization between data samples to be transmitted and a measured or observed transmission of the data samples. By comparing these blocks of data samples, DFE functions such as digital pre-distortion (DPD) parameter adaptation may be implemented. The hybrid architecture enables high flexibility at low additional cost. To further limit the costs, the programable processing array may have processing power and memory that is reduced compared to conventional processing array implementations.

公开(公告)号：US20230418781A1

公开(公告)日：2023-12-28

申请号：US17851739

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Kevin Kinney ,  Zoran Zivkovic

IPC: G06F15/80 ,  G06F1/12

CPC classification number: G06F15/80 ,  G06F1/12

Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture implements a data driven synchronization process to maintain synchronization between the programmable elements (PEs) of the programmable processing array. The hybrid architecture implements a timer-based solution to ensure data-driven synchronization between the PEs of the programmable processing array meets the time-based synchronization requirements of the overall system. The timers function to introduce a delay or latency to the time required by each of the PEs of the programmable processing array to perform their respective tasks, thereby forcing the hardware blocks to wait to receive the processed data samples output via the PEs and perform their hardware-based computations.