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1.发明公开公开(公告)号：US20240008045A1
公开(公告)日：2024-01-04
申请号：US17853194
申请日：2022-06-29
Applicant: Intel Corporation
Inventor： Kannan Rajamani , Kameran Azadet , Kevin Kinney , Thomas Smith , Zoran Zivkovic
CPC classification number: H04W72/042 , H04J3/0661
Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture functions to maintain synchronization between data samples to be transmitted and a measured or observed transmission of the data samples. By comparing these blocks of data samples, DFE functions such as digital pre-distortion (DPD) parameter adaptation may be implemented. The hybrid architecture enables high flexibility at low additional cost. To further limit the costs, the programable processing array may have processing power and memory that is reduced compared to conventional processing array implementations.
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公开(公告)号：US20240004957A1
公开(公告)日：2024-01-04
申请号：US17854095
申请日：2022-06-30
Applicant: Intel Corporation
Inventor： Sunitha Motipalli , Kameran Azadet , Albert Molina , Joseph Othmer , Kannan Rajamani
IPC: G06K9/00
CPC classification number: G06K9/0053 , G06K9/0055
Abstract: Techniques are disclosed for the use of Crest Factor Reduction (CFR) algorithm that performs oversampling of an input signal and a cancellation pulse, and detects a set of peak samples in the upsampled input signal that exceed a predetermined threshold value. The peak samples are clustered such that a subset of the oversampled signal peaks are used to compute gain factors for the generation of a scaled truncated upsampled cancellation pulse. Several scaled truncated upsampled cancellation pulses are applied in parallel to perform peak cancellation of the highest peak in each cluster as part of an initial peak cancellation process. Any remaining peaks are canceled by iterative gain factors computation process. A final cancellation pulse is then generated by multiplying a cancellation pulse by the computed gain factors.
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公开(公告)号：US09262350B2
公开(公告)日：2016-02-16
申请号：US14052911
申请日：2013-10-14
Applicant: Intel Corporation
Inventor： Kannan Rajamani , Ramon Sanchez , Kevin R. Kinney
CPC classification number: G06F13/1647 , H03M13/27 , H04L1/00 , H04L1/0045 , H04L1/0068 , H04L1/0071 , H04L1/1835
Abstract: One embodiment is an apparatus having a memory, a controller, and a de-interleaving module. The memory is configured to store portions of a set of interleaved values, where the set of interleaved values correspond to a single application of an interleaving mapping to a set of un-interleaved values. The controller is configured to retrieve each portion from an other memory that stores the set of interleaved values by moving the portion from the other memory to the memory. The de-interleaving module is configured to de-interleave the interleaved values in at least one of the portions to generate a de-interleaved portion such that processing downstream of the de-interleaving module can begin processing the de-interleaved portion before all of the interleaved values in the set of interleaved values are de-interleaved by the de-interleaving module.
Abstract translation: 一个实施例是具有存储器，控制器和解交织模块的装置。 存储器被配置为存储一组交织值的部分，其中交织的值集合对应于一组未交织值的交织映射的单个应用。 控制器被配置为通过将从另一存储器的部分移动到存储器来从存储该组交错值的其他存储器检索每个部分。 解交织模块被配置为对至少一个部分中的交织值进行解交织以产生解交织部分，使得解交织模块的下游处理可以在所有解交织部分之前开始处理去交错部分 交错值组中的交织值由解交织模块进行解交织。
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Patent Agency Ranking
4.发明公开公开(公告)号：US20240220445A1
公开(公告)日：2024-07-04
申请号：US18147829
申请日：2022-12-29
Applicant: Intel Corporation
Inventor： Kannan Rajamani , Kameran Azadet , Kevin Kinney , Thomas Smith , Zoran Zivkovic
CPC classification number: G06F15/80 , G06F9/5027 , G06F9/54
Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture functions to maintain synchronization between data samples to be transmitted, feedback data samples measured from an observed previous transmission of data samples, and output data samples that comprise the data samples from previous data transmissions, which may include data samples prior to or after the application of DPD terms. The architecture enables synchronization amongst several transmission channels, and provides for high flexibility with respect to timing flows and the movement and processing of data blocks.
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公开(公告)号：US12003248B2
公开(公告)日：2024-06-04
申请号：US17131819
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Matteo Camponeschi , Albert Molina , Kannan Rajamani , Giacomo Cascio , Christian Lindholm
CPC classification number: H03M1/1009 , H04B1/40 , H04L5/0048
Abstract: A method and system for controlling an analog-to-digital converter (ADC) in an observation path in a transceiver. The transceiver includes a transmit path, a receive path, and an observation path. The observation path includes an analog buffer and an observation ADC. A controller generates a control signal to control sampling events at the observation ADC to activate the observation ADC at combined uniform and non-uniform sampling instants. The controller may also generate a second control signal indicating whether digital data obtained by the observation ADC is valid or not. The digital data generated by the observation ADC at non-uniform sampling instants is indicated as invalid and digital data generated by the observation ADC at uniform sampling instants is indicated as valid. The digital data indicated as invalid may be discarded and the digital data indicated as valid is used for calibration of the transmit path or the receive path.
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公开(公告)号：US20230205730A1
公开(公告)日：2023-06-29
申请号：US17560637
申请日：2021-12-23
Applicant: Intel Corporation
Inventor： Zoran Zivkovic , Kameran Azadet , Kannan Rajamani , Thomas Smith
CPC classification number: G06F15/8092 , G06F17/11
Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture dedicates the most computationally intensive blocks to the hardware accelerator, while maintaining flexibility for additional computations to be performed by the programmable processing array. An interface is also described for coupling the processing array to the hardware accelerator, which achieves a division of functionality and connects the programmable processing array components to the hardware accelerator components without sacrificing flexibility. This results in a balance between power/area and flexibility.
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7.发明公开公开(公告)号：US20230205727A1
公开(公告)日：2023-06-29
申请号：US17560685
申请日：2021-12-23
Applicant: Intel Corporation
Inventor： Zoran Zivkovic , Kameran Azadet , Kannan Rajamani , Thomas Smith
Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture dedicates the most computationally intensive blocks to the hardware accelerator, which may be implemented for the computation of pre-distortion (DPD) coefficients while maintaining flexibility for additional DPD computations to be performed by the programmable processing array. An interface is also described for coupling the processing array to the hardware accelerator, which achieves a division of functionality and connects the programmable processing array components to the hardware accelerator components without sacrificing flexibility. This results in a balance between power/area and flexibility.
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公开(公告)号：US20240007337A1
公开(公告)日：2024-01-04
申请号：US17854155
申请日：2022-06-30
Applicant: Intel Corporation
Inventor： Sunitha Motipalli , Kameran Azadet , Albert Molina , Joseph Othmer , Kannan Rajamani
IPC: H04L27/26
CPC classification number: H04L27/2618 , H04L27/262 , H04L27/2615 , H04B1/0475
Abstract: Techniques are disclosed for the use of Crest Factor Reduction (CFR) technique that utilizes a cancellation pulse signal having a reduced length. The CFR technique may be applied to a signal to be transmitted, which may comprise a composite signal having one or more carrier signals. Each carrier signal of the composite signal may be filtered via a respective channel filter and then recombined to form the signal to be transmitted, on which the CFR operations are then applied. The length of the cancellation pulse signal is less than the number of taps of the channel filter with the largest number of taps. This reduction in cancellation pulse signal length significantly reduces the processing power required to perform the CFR operations while maintaining regulatory emissions compliance.
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