公开(公告)号：US09262350B2

公开(公告)日：2016-02-16

申请号：US14052911

申请日：2013-10-14

Applicant: Intel Corporation

Inventor： Kannan Rajamani ,  Ramon Sanchez ,  Kevin R. Kinney

IPC: G06F13/16 ,  H03M13/27 ,  H04L1/00

CPC classification number: G06F13/1647 ,  H03M13/27 ,  H04L1/00 ,  H04L1/0045 ,  H04L1/0068 ,  H04L1/0071 ,  H04L1/1835

Abstract: One embodiment is an apparatus having a memory, a controller, and a de-interleaving module. The memory is configured to store portions of a set of interleaved values, where the set of interleaved values correspond to a single application of an interleaving mapping to a set of un-interleaved values. The controller is configured to retrieve each portion from an other memory that stores the set of interleaved values by moving the portion from the other memory to the memory. The de-interleaving module is configured to de-interleave the interleaved values in at least one of the portions to generate a de-interleaved portion such that processing downstream of the de-interleaving module can begin processing the de-interleaved portion before all of the interleaved values in the set of interleaved values are de-interleaved by the de-interleaving module.

Abstract translation: 一个实施例是具有存储器，控制器和解交织模块的装置。 存储器被配置为存储一组交织值的部分，其中交织的值集合对应于一组未交织值的交织映射的单个应用。 控制器被配置为通过将从另一存储器的部分移动到存储器来从存储该组交错值的其他存储器检索每个部分。 解交织模块被配置为对至少一个部分中的交织值进行解交织以产生解交织部分，使得解交织模块的下游处理可以在所有解交织部分之前开始处理去交错部分 交错值组中的交织值由解交织模块进行解交织。