公开(公告)号：US20220286736A1

公开(公告)日：2022-09-08

申请号：US17825795

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Palanivel Guruva Reddiar ,  Aswin Padmanabhan ,  Kiran K. Velicheti ,  Addicam V. Sanjay

IPC: H04N21/44 ,  G06F3/14 ,  H04N19/107 ,  H04N19/172 ,  H04N21/414 ,  H04N21/2187 ,  H04N21/81

Abstract: In one embodiment, an electronic device includes a video-in interface, a video-out interface, memory circuitry, and processing circuitry. A first video stream with uncompressed frames is received via the video-in interface. The first video stream is compressed and then stored in a video buffer on the memory circuitry. For example, the uncompressed frames are individually compressed and stored in the video buffer. A second video stream with encoded frames is decoded and then played on a display device. For example, the encoded frames are decoded and then displayed on the display device via the video-out interface. The first video stream is then decompressed and played on the display device. For example, the compressed frames in the video buffer are individually decompressed and then displayed on the display device via the video-out interface.

公开(公告)号：US20220004351A1

公开(公告)日：2022-01-06

申请号：US17481572

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Aswin Padmanabhan ,  Sangeeta Ghangam Manepalli ,  Kiran K. Velicheti ,  Robert James Johnston ,  Chandra Konduru ,  Todd M. Witter

IPC: G06F3/14 ,  H04N5/05

Abstract: In one embodiment, a processing device includes a plurality of display interfaces, a plurality of display controllers, and display synchronization circuitry. The display interfaces are used to interface with a plurality of display devices, and the display controllers are used to output video frames to the display devices via the display interfaces. Moreover, the display synchronization circuitry includes a clock synchronization interface and a frame synchronization interface. The clock synchronization interface is used to synchronize a clock rate across the display controllers, while the frame synchronization interface is used to synchronize a frame rate across the display controllers.

公开(公告)号：US20240064202A1

公开(公告)日：2024-02-22

申请号：US18497839

申请日：2023-10-30

Applicant: Intel Corporation

Inventor： Kishore Kasichainula ,  Aswin Padmanabhan ,  Satyeshwar Singh ,  Karthik Tyamgondlu ,  Marcos Paulo Da Silva

IPC: H04L67/1095 ,  G06F15/173 ,  H04L12/46

CPC classification number: H04L67/1095 ,  G06F15/17331 ,  H04L12/4645

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed. An example apparatus to synchronize event data includes first circuitry to implement a user interface controller. The user interface controller of the example apparatus is to detect a user input, transmit a message including event data to a network interface controller (NIC), the event data corresponding to the user input, and provide the event data to a driver to cause an event corresponding to the event data to be rendered by the apparatus. The example apparatus also includes second circuitry to implement the NIC. The NIC of the example apparatus is to store the event data from the message in a local buffer of the NIC, obtain the event data from the local buffer using a direct memory access (DMA) request, and transmit a packet including the event data over a network.

公开(公告)号：US20220116678A1

公开(公告)日：2022-04-14

申请号：US17556497

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Karthik Tyamgondlu ,  Benjamin Thomas Cope ,  Satyeshwar Singh ,  Sangeeta Ghangam Manepalli ,  Aswin Padmanabhan

IPC: H04N21/43 ,  H03L7/08

Abstract: In one embodiment, video content displayed across a plurality of display devices is synchronized by first obtaining a first set of VSYNC timestamps for a display controller of a first video display device and a second set of VSYNC timestamps for a display controller of a second video display device. An adjustment factor is determined based on a comparison of the first and second VSYNC timestamps, and an adjusted VSYNC period for the display controller of the second video display device is programmed based on the determined adjustment factor. After a predetermined number of VSYNC cycles, the display controller of the second video display device reverts back to an original VSYNC period.

公开(公告)号：US12124759B2

公开(公告)日：2024-10-22

申请号：US17481572

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Aswin Padmanabhan ,  Sangeeta Ghangam Manepalli ,  Kiran K. Velicheti ,  Robert James Johnston ,  Chandra Konduru ,  Todd M. Witter

IPC: G06F3/14

CPC classification number: G06F3/1446

Abstract: In one embodiment, a processing device includes a plurality of display interfaces, a plurality of display controllers, and display synchronization circuitry. The display interfaces are used to interface with a plurality of display devices, and the display controllers are used to output video frames to the display devices via the display interfaces. Moreover, the display synchronization circuitry includes a clock synchronization interface and a frame synchronization interface. The clock synchronization interface is used to synchronize a clock rate across the display controllers, while the frame synchronization interface is used to synchronize a frame rate across the display controllers.

公开(公告)号：US20230262281A1

公开(公告)日：2023-08-17

申请号：US18296264

申请日：2023-04-05

Applicant: Intel Corporation

Inventor： Kishore Kasichainula ,  Aswin Padmanabhan ,  Satyeshwar Singh

IPC: H04N21/43

CPC classification number: H04N21/43076

Abstract: The present disclosure provides display network synchronization (sync) technologies and techniques using time-sensitive networking (TSN) and/or Precision Time Protocol (PTP) technologies. The display network sync mechanisms synchronize multiple display systems that are communicatively coupled together via a network. The display network sync mechanisms involve synchronizing the display systems with one another, synchronizing the various clocks and/or timers of each display system, monitoring clock drift of display clocks of individual display systems, and adjusting display signaling based on the monitored clock drift. The monitoring and adjusting of the display signaling can be accomplished without broadcasting the display signaling over the network connection.