公开(公告)号：US10235486B2

公开(公告)日：2019-03-19

申请号：US15279725

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Krishnan Srinivasan ,  Robert P. Adler ,  Robert De Gruijl ,  Jay Tomlinson ,  Eric A. Geisler

IPC: G06F17/50

Abstract: In one embodiment, a design tool for designing a system on chip (SoC) includes hardware logic to generate one or more configuration files for a fabric of a SoC to be designed by the design tool. This logic is configured, based at least in part on user input, to generate the one or more configuration files, according to at least one of: automatic derivation of all parameters of the fabric, according to a first user selection; manual input by a user of at least some parameters of the fabric and automatic derivation of at least other parameters of the fabric, according to a second user selection; and manual input by the user of the all parameters of the fabric, according to a third user selection. Other embodiments are described and claimed.

公开(公告)号：US10255399B2

公开(公告)日：2019-04-09

申请号：US15338639

申请日：2016-10-31

Applicant: Intel Corporation

Inventor： Krishnan Srinivasan ,  Robert P. Adler ,  Eric A. Geisler ,  Robert De Gruijl ,  Jay Tomlinson

IPC: G06F17/50 ,  G06F13/40 ,  G06F13/42 ,  H04L29/12

Abstract: In one embodiment, a design tool for designing a system on chip (SoC) includes hardware mapping logic to automatically generate a channel mapping for a path between a first intellectual property (IP) logic of the SoC and a second IP logic of the SoC. The hardware mapping logic, based at least in part on user input of a source channel associated with the first IP logic, a sink channel associated with the second IP logic and at least one derivation parameter, is to generate the channel mapping according to one of a plurality of derivation algorithms. Other embodiments are described and claimed.