公开(公告)号：US20190228821A1

公开(公告)日：2019-07-25

申请号：US16370028

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Wei Yee Koay ,  Rajiv Kumar ,  Pek Mui Goh ,  Kuan Cheng Tang ,  Wei Chieh Wong

IPC: G11C11/419 ,  H03K19/177 ,  G11C11/418 ,  G11C11/412

Abstract: A method for operating an SRAM of an FPGA in a high or low-power mode includes a CRAM of the FPGA storing control bits for controlling whether pages of the SRAM operate in the high or low-power mode. A control circuit of the FPGA uses the control bits, a system clock signal, and address for the pages to determine whether to operate the pages in the high or low-power mode and to control the timing for precharging and tristating read bitlines of the pages for the high and low-power modes. In the high-power mode the read bitlines are precharged longer than in the low-power mode, and in the high-power mode the read bitlines are tristated less than in the low-power mode. Precharging the read bitlines for a lesser time in the low-power mode reduces DC leakage current in the lower power mode compared to the high-power mode.