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    Techniques for preventing voltage tampering of security control circuits
    2.
    发明授权
    Techniques for preventing voltage tampering of security control circuits 有权

    公开(公告)号：US11443073B2

    公开(公告)日：2022-09-13

    申请号：US16222564

    申请日：2018-12-17

    Applicant: Intel Corporation

    Inventor： Wei Yee Koay ,  Ting Lu ,  Ching Kooi Hor ,  Chin Ghee Ch'ng

    IPC: G06F1/08 ,  H03K5/24 ,  H03K3/03 ,  H03K19/17768 ,  G06F21/76

    Abstract: An integrated circuit includes a comparator circuit that generates a control signal based on a comparison between a threshold voltage and a supply voltage. The integrated circuit also includes a clock signal generation circuit that generates a clock signal and that receives the control signal. The clock signal generation circuit decreases a frequency of the clock signal to a reduced frequency in response to the control signal indicating that the supply voltage has decreased below the threshold voltage. The integrated circuit also includes a secure device manager circuit that has a timing circuit. The clock signal is provided to a clock input of the timing circuit. The timing circuit receives supply current from the supply voltage. The secure device manager circuit performs a security function for the integrated circuit using the timing circuit in response to the clock signal with the reduced frequency.

    Techniques For Preventing Voltage Tampering Of Security Control Circuits
    5.
    发明申请
    Techniques For Preventing Voltage Tampering Of Security Control Circuits 审中-公开

    公开(公告)号：US20190138754A1

    公开(公告)日：2019-05-09

    申请号：US16222564

    申请日：2018-12-17

    Applicant: Intel Corporation

    Inventor： Wei Yee Koay ,  Ting Lu ,  Ching Kooi Hor ,  Chin Ghee Ch'ng

    IPC: G06F21/76 ,  H03K3/03 ,  H03K5/24 ,  G06F1/08

    Abstract: An integrated circuit includes a comparator circuit that generates a control signal based on a comparison between a threshold voltage and a supply voltage. The integrated circuit also includes a clock signal generation circuit that generates a clock signal and that receives the control signal. The clock signal generation circuit decreases a frequency of the clock signal to a reduced frequency in response to the control signal indicating that the supply voltage has decreased below the threshold voltage. The integrated circuit also includes a secure device manager circuit that has a timing circuit. The clock signal is provided to a clock input of the timing circuit. The timing circuit receives supply current from the supply voltage. The secure device manager circuit performs a security function for the integrated circuit using the timing circuit in response to the clock signal with the reduced frequency.

    EDGE DEVICES UTILIZING PERSONALIZED MACHINE LEARNING AND METHODS OF OPERATING THE SAME
    6.
    发明申请
    EDGE DEVICES UTILIZING PERSONALIZED MACHINE LEARNING AND METHODS OF OPERATING THE SAME 审中-公开

    公开(公告)号：US20190050683A1

    公开(公告)日：2019-02-14

    申请号：US16146860

    申请日：2018-09-28

    Applicant: Intel Corporation

    Inventor： Maruti Gupta Hyde ,  Florence Pon ,  Naissa Conde ,  Xue Yang ,  Wei Yee Koay

    IPC: G06K9/62 ,  G06N3/08 ,  G06F15/18 ,  G06F21/62

    Abstract: Edge devices utilizing personalized machine learning and methods of operating the same are disclosed. An example edge device includes a model accessor to access a first machine learning model from a cloud service provider. A local data interface is to collect local user data. A model trainer is to train the first machine learning model to create a second machine learning model using the local user data. A local permissions data store is to store permissions indicating constraints on the local user data with respect to sharing outside of the edge device. A permissions enforcer is to apply permissions to the local user data to create a sub-set of the local user data to be shared outside of the edge device. A transmitter is to provide the sub-set of the local user data to a public data repository.

    Automated loading services for computer assisted or autonomous driving vehicles
    9.
    发明授权
    Automated loading services for computer assisted or autonomous driving vehicles 有权

    公开(公告)号：US11104529B2

    公开(公告)日：2021-08-31

    申请号：US16140479

    申请日：2018-09-24

    Applicant: Intel Corporation

    Inventor： Lady Nataly Pinilla Pico ,  Melissa M. Ortiz ,  Gayathri Jeganmohan ,  Wei Yee Koay ,  Shahrnaz Azizi ,  Rita H. Wouhaybi

    IPC: G05D1/00 ,  B65G67/04 ,  G05D1/02

    Abstract: Embodiments include apparatuses, methods, and systems to provide an automated loading device to a computer assisted or autonomous driving (CA/AD) vehicle. A loading service control device is to initiate a loading service to load one or more items into a storage space of a CA/AD vehicle, using an automated loading device. A CA/AD vehicle is to move to a loading area at an appointed time. A mechanical loading unit of an automated loading device is to place one or more items into a storage space of a CA/AD vehicle. A user device is to receive an input from a user, where the input includes information to generate a request to a loading service control device to load one or more items into a storage space of a CA/AD vehicle using an automated loading device. Other embodiments may also be described and claimed.

    Programmable High-Speed and Low-power Mode FPGA Memory with Configurable Floating Bitlines Scheme
    10.
    发明申请
    Programmable High-Speed and Low-power Mode FPGA Memory with Configurable Floating Bitlines Scheme 审中-公开

    公开(公告)号：US20190228821A1

    公开(公告)日：2019-07-25

    申请号：US16370028

    申请日：2019-03-29

    Applicant: Intel Corporation

    Inventor： Wei Yee Koay ,  Rajiv Kumar ,  Pek Mui Goh ,  Kuan Cheng Tang ,  Wei Chieh Wong

    IPC: G11C11/419 ,  H03K19/177 ,  G11C11/418 ,  G11C11/412

    Abstract: A method for operating an SRAM of an FPGA in a high or low-power mode includes a CRAM of the FPGA storing control bits for controlling whether pages of the SRAM operate in the high or low-power mode. A control circuit of the FPGA uses the control bits, a system clock signal, and address for the pages to determine whether to operate the pages in the high or low-power mode and to control the timing for precharging and tristating read bitlines of the pages for the high and low-power modes. In the high-power mode the read bitlines are precharged longer than in the low-power mode, and in the high-power mode the read bitlines are tristated less than in the low-power mode. Precharging the read bitlines for a lesser time in the low-power mode reduces DC leakage current in the lower power mode compared to the high-power mode.

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