公开(公告)号：US20190228821A1

公开(公告)日：2019-07-25

申请号：US16370028

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Wei Yee Koay ,  Rajiv Kumar ,  Pek Mui Goh ,  Kuan Cheng Tang ,  Wei Chieh Wong

IPC: G11C11/419 ,  H03K19/177 ,  G11C11/418 ,  G11C11/412

Abstract: A method for operating an SRAM of an FPGA in a high or low-power mode includes a CRAM of the FPGA storing control bits for controlling whether pages of the SRAM operate in the high or low-power mode. A control circuit of the FPGA uses the control bits, a system clock signal, and address for the pages to determine whether to operate the pages in the high or low-power mode and to control the timing for precharging and tristating read bitlines of the pages for the high and low-power modes. In the high-power mode the read bitlines are precharged longer than in the low-power mode, and in the high-power mode the read bitlines are tristated less than in the low-power mode. Precharging the read bitlines for a lesser time in the low-power mode reduces DC leakage current in the lower power mode compared to the high-power mode.

公开(公告)号：US20240337692A1

公开(公告)日：2024-10-10

申请号：US18746853

申请日：2024-06-18

Applicant: Intel Corporation

Inventor： Rajiv Kumar ,  Amit Agarwal ,  Steven Hsu ,  Scott Weber

IPC: G01R31/3185

CPC classification number: G01R31/318541 ,  G01R31/318572

Abstract: A flip-flop circuit includes first and second storage circuits. The flip-flop circuit is configurable to store first values of a data signal in the first storage circuit in response to rising edges of a clock signal and to store second values of the data signal in the second storage circuit in response to falling edges of the clock signal during a double edge triggered mode. The flip-flop circuit is configurable to store third values of the data signal in the first storage circuit and to output the third values from the first storage circuit in response to the clock signal during a single edge triggered mode.

公开(公告)号：US20230131938A1

公开(公告)日：2023-04-27

申请号：US18085819

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Scott Weber ,  Chang Kian Tan ,  Rajiv Kumar ,  Saravanan Sethuraman

IPC: G06F3/06

Abstract: An integrated circuit includes a buffer circuit, a memory circuit, and a controller circuit that determines if the memory circuit stores information that is valid and determines whether to transmit the information stored in the memory circuit to the buffer circuit based on credits that indicate an amount of storage space available in the buffer circuit. The controller circuit transmits the information to the buffer circuit if the credits indicate that sufficient storage space is available in the buffer circuit to store the information.