公开(公告)号：US20210066232A1

公开(公告)日：2021-03-04

申请号：US17098754

申请日：2020-11-16

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Sri Ranga Sai Boyapati ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Javier Soto Gonzalez ,  Kwangmo Chris Lim ,  Aleksandar Aleksov

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/13 ,  H01L21/48

Abstract: Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented.

公开(公告)号：US11532584B2

公开(公告)日：2022-12-20

申请号：US17098754

申请日：2020-11-16

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Sri Ranga Sai Boyapati ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Javier Soto Gonzalez ,  Kwangmo Chris Lim ,  Aleksandar Aleksov

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/13 ,  H01L21/48 ,  H01L25/065

Abstract: Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented.