公开(公告)号：US20250006645A1

公开(公告)日：2025-01-02

申请号：US18343892

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Xiao Liu ,  Bohan Shan ,  Dingying Xu ,  Gang Duan ,  Haobo Chen ,  Hongxia Feng ,  Jung Kyu Han ,  Xiaoying Guo ,  Zhixin Xie ,  Xiyu Hu ,  Robert Alan May ,  Kristof Kuwawi Darmawikarta ,  Changhua Liu ,  Yosuke Kanaoka

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/58 ,  H01L25/10

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer of a substrate including a first material having a cavity and a conductive pad at a bottom of the cavity; a first microelectronic component having a first surface and an opposing second surface, the first microelectronic component in the cavity and electrically coupled to the conductive pad at the bottom of the cavity; a second layer of the substrate on the first layer of the substrate, the second layer including a second material that extends into the cavity and on and around the first microelectronic component, wherein the second material includes an organic photoimageable dielectric (PID) or an organic non-photoimageable dielectric (non-PID); and a second microelectronic component electrically coupled to the second surface of the first microelectronic component by conductive pathways through the second layer of the substrate.

公开(公告)号：US12176292B2

公开(公告)日：2024-12-24

申请号：US18375867

申请日：2023-10-02

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US12040276B2

公开(公告)日：2024-07-16

申请号：US17888177

申请日：2022-08-15

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Wei-Lun Kane Jen ,  Jonathan L. Rosch ,  Islam A. Salama ,  Kristof Darmawikarta

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/16227

Abstract: A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

公开(公告)号：US20240128138A1

公开(公告)日：2024-04-18

申请号：US18392368

申请日：2023-12-21

Applicant: Intel Corporation

Inventor： Robert L. Sankman ,  Rahul N. Manepalli ,  Robert Alan May ,  Srinivas Venkata Ramanuja Pietambaram ,  Bharat P. Penmecha

IPC: H01L23/15 ,  H01L21/48 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/15 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5384 ,  H01L25/0655

Abstract: Semiconductor packages and methods for forming semiconductor packages are disclosed. An example semiconductor package includes a substrate and a core. An insulator material is present over the core, and along a direction perpendicular to a first surface of the core, a portion of the insulator material is between the core and a first surface of the substrate. A via extends between the first surface of the core and a second surface of the core in the direction perpendicular to the first surface of the core. A bridge die is in a recess in the substrate. The bridge die is coupled with the via. An electronic component is coupled to an end of the via at a second surface of the substrate.

公开(公告)号：US20240112972A1

公开(公告)日：2024-04-04

申请号：US17958002

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Hiroki Tanaka ,  Robert Alan May ,  Kristof Darmawikarta ,  Bai Nie ,  Brandon C. Marin ,  Jeremy D. Ecton ,  Srinivas Venkata Ramanuja Pietambaram ,  Changhua Liu

IPC: H01L23/15 ,  G02B6/42 ,  G02B6/43

CPC classification number: H01L23/15 ,  G02B6/4204 ,  G02B6/4259 ,  G02B6/426 ,  G02B6/43

Abstract: Disclosed herein are microelectronics package architectures utilizing photo-integrated glass interposers and photonic integrated glass layers and methods of manufacturing the same. The microelectronics packages may include an organic substrate, a photonic integrated glass layer, and a glass interpose. The organic substrate may define through substrate vias. The photonic integrated glass layer may be attached to the organic substrate. The photonic integrated glass layer may include photo detectors. The glass interposer may be attached to the organic substrate. The glass interposer may define through glass vias in optical communication with the photo detectors.

公开(公告)号：US11901296B2

公开(公告)日：2024-02-13

申请号：US18089540

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Kristof Darmawikarta ,  Sri Ranga Sai Sai Boyapati

IPC: H01L23/532 ,  H01L23/29 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00 ,  H01L23/50 ,  H01L21/48

CPC classification number: H01L23/5329 ,  H01L23/293 ,  H01L23/5226 ,  H01L21/4853 ,  H01L23/50 ,  H01L23/5381 ,  H01L23/5385 ,  H01L24/19 ,  H01L24/25

Abstract: A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect. The bridge die is embedded in the multilayer substrate structure. The substrate interconnect extends from a level above the bridge die to a level below the bridge die. The multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material. The multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material.

公开(公告)号：US11302643B2

公开(公告)日：2022-04-12

申请号：US16829396

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US10978399B2

公开(公告)日：2021-04-13

申请号：US16474589

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Robert Alan May ,  Sri Ranga Sai Sai Boyapati ,  Wei-Lun Kane Jen ,  Javier Soto Gonzalez

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/768 ,  H01L23/13 ,  H01L23/495 ,  H01L23/532

Abstract: A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect, wherein the bridge die is embedded in the multilayer substrate structure. The die interconnect substrate comprises a via portion formed on the first bridge die pad of the bridge die. An average angle between a surface of the first bridge die pad and a sidewall of the via portion lies between 85° and 95°.

公开(公告)号：US20190355642A1

公开(公告)日：2019-11-21

申请号：US16335527

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Chi-Mon Chen ,  Robert Alan May ,  Amanda E. Schuckman ,  Wei-Lun Kane Jen

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/367 ,  H01L23/538 ,  H01L21/56

Abstract: Various embodiments disclosed relate to semiconductor device and method of making the same using functional silanes. In various embodiments, the present invention provides a semiconductor device including a silicon die component having a first silica surface. The semiconductor device includes a dielectric layer having a second surface generally facing the first silica surface. The semiconductor device includes an interface defined between the first surface and the second surface. The semiconductor device also includes a silane based adhesion promoter layer disposed within the junction and bonded to at least one of the first silica surface and the dielectric layer second surface.

公开(公告)号：US20190198445A1

公开(公告)日：2019-06-27

申请号：US16182277

申请日：2018-11-06

Applicant: Intel Corporation

Inventor： Amruthavalli Pallavi Alur ,  Sri Ranga Sai Boyapati ,  Robert Alan May ,  Islam A. Salama ,  Robert L. Sankman

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/18 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L21/66 ,  H01L21/683 ,  H01L23/492 ,  H01L25/11

Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.